Texas Instruments Corporation

Ramtron International Corporation

Cypress Semiconductor Corporation

Jarrod Eliason

Anand Seshadri

Bill Kraus

Sudhir Kumar Madan

Xiao Hong Du

Yunchen Qiu

Hugh Pryor McAdams

Sung-Wei Lin

Richard Allen Bailey

William F Kraus

Glen Richard Fox

Scott Robert Summerfelt

Theodore Sidney Moise

Terence G Blake

Fan Chu

John Y Fong

Philip Rochette

Lawrence Teresi

Edwin Cezar Jabillo

A device including a ferroelectric memory and methods of manufacturing the same are provided. In one embodiment, the device includes a semiconductor die with an integrated circuit fabricated thereon, a stress buffer die mounted to the semiconductor die overlying the integrated circuit, and a molding compound encapsulating the semiconductor die and the stress buffer die. Generally the integrated circuit includes a ferroelectric memory. In some embodiments, the device further includes a polyimide layer between the stress buffer and the semiconductor die. Other embodiments are also provided.

Ferroelectric memories with a stress buffer

Ferroelectric memory cells () are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell () is not being accessed while avoiding significant disruption of memory cell access operations. Methods () are provided for fabricating ferroelectric memory cells () and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material () or in an encapsulation layer () formed over the patterned capacitor structure (C).

Ferroelectric capacitor with parallel resistance for ferroelectric memory

Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Accelerated low power fatigue testing of FRAM

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to its source to turn if off during boostenig. Transistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuits

Reference generator systems () and methods () are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (). The reference generator system () comprises a primary capacitance (), a precharge system () that charges the primary capacitance, and a reference system () with a plurality of local reference circuits () associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S) coupled between the staging capacitance and the primary capacitance (), and a second switching device (S, S) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S) couples the staging capacitance (Cs) to the precharged primary capacitance () and then isolates the precharged staging capacitance (Cs) from the primary capacitance (), and the second switching device (S, S) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.

Ferroelectric memory reference generator systems using staging capacitors

Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Method and apparatus to reduce storage node disturbance in ferroelectric memory

Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to the cells of the configuration data rows. This allows at least some of the circuitry utilized to access data from the primary array to be utilized to access the configuration data, which promotes an efficient use of resources among other things. Additionally, the configuration data can be transferred to volatile registers serially at startup to simplify routing and design and thereby conserve space. The volatile registers are operatively associated with configuration data circuitry that makes use of the configuration data at startup or later time(s).

High reliability area efficient non-volatile configuration data storage for ferroelectric memories

A SRAM cell wherein the pull up load of the cell is inherent ferroelectric leakage. The power down writeback may include boosting the word line. The power down writeback may also include discharging the plate from Vto ground. Furthermore, the plate is held high during read and write operations.

Non-volatile SRAM

Ferroelectric memory devices and control circuits therefor are presented, in which memory array control and timing signals are derived according to tap outputs from a group of series connected delay elements. Some or all of the individual delay elements comprise one or more trim inputs and a variable delay circuit that provides an output signal a variable delay time after the delay element input signal, where the variable delay is set according to the trim inputs, allowing the control signals to be adjusted or trimmed to accommodate fabrication process variations.

Delay system for generating control signals in ferroelectric memory devices

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to ists source to turn if off during boostenig. Ttransistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuit

Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Ferroelectric non-volatile logic elements

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN) to charge the boosting capacitor (C) to VDD at the end of each memory access and to use a PMOS FET (MPMP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Programmable reference for 1T/1C ferroelectric memories

Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The ferroelectric capacitor residing over the first and second circuit elements, and first and second contacts, has a conductive plate that may be used as a local interconnect layer. The conductive plate extends between and electrically couples first and second circuit elements directly through first and second contacts of the ferroelectric memory device. Methods are also provided for forming the local interconnect layer within the conductive plate of the ferroelectric capacitor.

Growing community of inventors

Colorado Springs, CO, United States of America

Jarrod Eliason