International Business Machines Corporation

University of Michigan

William Marsh Rice University

Jarrod Alexander Roy

Charles Jay Alpert

Gi-Joon Nam

Wael R El-Essawy

Zhuo Li

Shyam Ramji

Natarajan Viswanathan

Paul Gerard Villarrubia

Juan C Rubio

Thomas W Keller, Jr

David Anthony Papa

Taraneh Taghavi

Lakshmi Narasimha Reddy

Gustavo Enrique Tellez

Farinaz Koushanfar

Igor L Markov

Andrew D Huber

Dorothy Kucar

Wael R Ei-Essawy

Natarajan Vishvanathan

A mechanism is provided for automatically routing network interconnects in a data processing system. A processor in a node of a plurality of nodes receives network topology from neighboring nodes in the plurality of nodes within the data processing system. The processor constructs a system node map that identifies a physical connectivity between the node and the neighboring nodes. The processor programs a switch in the node with a connectivity map that indicates a set of point-to-point connections with the neighboring nodes. The set of point-to-point connections comprise locally-connected connections and pass-through connections.

Automatically routing super-compute interconnects

A processing module is provided that comprises a set of processing module sides, each comprising a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side couples to another processing module side to form a modular processing module. The modular processing module comprises an exterior connection to a power source and a communication system and a plurality of cold plates coupled to the plurality of processing nodes. Liquid coolant is circulated through the plurality of cold plates via a closed loop by at least one pump through a plurality of tubes and through at least one heat exchanger. The at least one heat exchanger is coupled to an exterior portion of the processing module. The at least one heat exchanger cools the liquid coolant using air surrounding the processing module.

Liquid cooling system for stackable modules in energy-efficient computing systems

A computing system is provided. In the computing system, a plurality of modules physically arranged in a three dimensional hexadron configuration. In the computing system, the at least one module is either a liquid-tight module filled with a non-conductive liquid coolant or a module cooled with a liquid coolant circulating through cold plates mounted on electronic components. In the computing system, the liquid coolant is circulated in a closed loop by at least one pump through a plurality of hoses through at least one of a plurality of heat exchangers. In the computing system, the plurality of heat exchangers is coupled to an exterior portion of the surface of the computing system. In the computing system, the plurality of heat exchangers cool the liquid coolant through tinned tubes exposed to the surrounding air.

A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

Post-placement cell shifting

Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.

Protecting hardware circuit design by secret sharing

A mechanism is provided for determining connectivity while minimizing wiring in an electronic system. The mechanism identifies a configuration of the electronic system, a location of each module in a plurality of modules within the electronic system and at least one constraint with regard to wiring the electronic system, the location of each module being identified using three-dimensional coordinates. The mechanism routes a separate cable from each module in the plurality of modules to each of the other modules in the plurality of modules without violating any constraints, thereby forming a plurality of cables. The mechanism then generates a cabling list indicating how each cable in the plurality of cables is to be routed in the electronic system in order to not violate any constraints and provide connectivity while minimizing wiring.

Minimizing the maximum required link capacity for three-dimensional interconnect routing

A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.

Routing-based pin placement

A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

Detailed routability by cell placement

Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.

Incremental timing optimization and placement

A computing system is provided. In the computing system, a plurality of modules physically arranged in a three dimensional hexadron configuration. In the computing system, the at least one module is either a liquid-tight module filled with a non-conductive liquid coolant or a module cooled with a liquid coolant circulating through cold plates mounted on electronic components. In the computing system, the liquid coolant is circulated in a closed loop by at least one pump through a plurality of hoses through at least one of a plurality of heat exchangers. In the computing system, the plurality of heat exchangers is coupled to an exterior portion of the surface of the computing system. In the computing system, the plurality of heat exchangers cool the liquid coolant through finned tubes exposed to the surrounding air.

A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

Growing community of inventors

Austin, TX, United States of America

Jarrod Alexander Roy