Ihp Gmbh - Innovations for High Performance Microelectronics

Ihp Gmbh-innovations for High Performance Microelectronics/leibniz-institut Fur Innovative Mikroelektronik

Jaroslaw Dabrowski

Grzegorz Lupina

Gunther Lippert

Wolfgang Mehr

Johann Christoph Scheytt

Chafik Meliani

Olaf Seifarth

Andre Wolff

Christian Wenger

Max Lemme

Mindaugas Lukosius

André Wolff

A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.

Graphene base transistor and method for making the same

A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.

Graphene base transistor having compositionally-graded collector barrier layer

A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.

P-type graphene base transistor

A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.

Fabrication of graphene electronic devices using step surface contour

Growing community of inventors

Frankfurt-am-Main, Germany

Jaroslaw Dabrowski