Motorola Corporation

Motorla, Inc.

Jaroslaw A Magera

Gregory Joseph Dunn

Jovica Savic

Kathy D Leganski

Aroon V Tungare

Robert T Croswell

Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

Printed circuit board having closed vias

A sequentially laminated printed circuit board having highly reliable vias can be fabricated by pattern plating flanges or via lands on a copper foil, laminating the foil to a prepreg so that the flanges are embedded into the surface of the prepreg, creating via holes in the laminate that are substantially concentric with the individual flanges, plating the via holes with copper, chemically or mechanically milling off a portion of the copper plating and optionally some of the copper foil to reduce the overall thickness of the laminate, and laminating a second and optionally a third prepreg to the laminate. The resulting printed circuit board has the flanges embedded in the surface of the laminate so that the inside wall of the flange is electrically and mechanically attached to the outside wall of the plated through hole barrel.

Printed circuit board

Fabricating () a printed circuit board includes fabricating patterned conductive traces () onto a foil, laminating the patterned conductive traces to a printed circuit board substrate () by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling () and/or etching ().

Method for fabricating a printed circuit board

A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

Method for fabricating closed vias in a printed circuit board

A method is for fabricating an embedded capacitance printed circuit board assembly (). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (). Each capacitance structure () includes a crystallized dielectric oxide layer () sandwiched between an outer electrode layer () and an inner electrode layer () in which the two inner electrode layers are electrically connected together. A rivet via () and a stacked via () formed from a button via () and a stacked blind via () may be used to electrically connect the two inner electrode layers together. A spindle via () may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate () that includes two capacitance structures.

Capacitance laminate and printed circuit board apparatus and method

A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating () a ceramic oxide layer () overlying a conductive metal layer () overlying a printed circuit substrate (), perforating () the ceramic oxide layer within a region (), and removing () the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

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Palatine, IL, United States of America

Jaroslaw A Magera