Intel Corporation

Jared W Stark

Ahmad Yasin

Lihu Rappoport

Ajay Amarsingh Singh

Zeev Sperber

Hong Wang

Christopher B Wilkerson

Stanislav Shwartsman

Igor Yanover

John P Shen

Gideon Gerzon

Israel Diamand

Ibrahim Hur

Ryan N Rakvic

George Leifman

Gadi Haber

Alex Gerber

Andrey Kluchnikov

Pavel I Kryukov

Kamil Garifullin

Nir Tell

Bohuslav Rychlik

Jeffrey Baxter

Amjad Aboud

Gal Diskin

Pavel Fridman

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

Code prefetch instruction

Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

Selective use of branch prediction hints

A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

Instruction and logic for register based hardware memory renaming

A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

Non-vital loads

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Santa Clara, CA, United States of America

Jared W Stark