Intel Corportion

Jared Pager

Christopher J Nelson

James Edward Neeb

Timothy J Callahan

Bradly L Inman

Stephen Sturges

Shelby G Rollins

Sundar V Pathy

Matthew Hendricks

Hiren V Tilala

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Compressed test patterns for a field programmable gate array

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Portland, OR, United States of America

Jared Pager