International Business Machines Corporation

Globalfoundries Inc.

Jared P Yanofsky

Andrew H Norfleet

Nicholas G Clore

Stephen Peter Ayotte

Heather M Truax

Eric D Marz

Kendra A Lyons

Matthew G Bausch

Benjamin J Pierce

According to embodiments of the present invention, a semiconductor substrate is formed on at least a portion of a surface of a semiconductor substrate. The emitting layer is excited for a first predetermined time period. A first luminescent intensity value of the emitting layer is determined. In response to exposing the semiconductor substrate and the emitting layer to a condition for a second predetermined time period, a second luminescent intensity value of the emitting layer is determined. A thermal profile of at least the portion of the surface of the semiconductor substrate is determined utilizing the first luminescent intensity value and the second luminescent intensity value of the emitting layer. The thermal profile at least reflects information about one or more of the condition and the semiconductor substrate subsequent to exposure to the condition.

Determining thermal profiles of semiconductor structures

Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip).

Chip carrier with dual-sided chip access and a method for testing a chip using the chip carrier

Various embodiments include localized hardening of dicing channels in an integrated circuit (IC) wafer. In some embodiments, a method includes: applying localized heat to a metal interconnect in a wafer kerf on an IC wafer using a heat source; and removing the heat source to cool the metal interconnect after the applying of the localized heat to the metal interconnect, wherein the applying of the heat and the removing of the heat source increases a hardness of the metal interconnect.

Methods of localized hardening of dicing channel by applying localized heat in wafer kerf

Systems and methods are provided for developing usable chip images in order to detect and screen defects or anomalies in a manufacturing environment. More specifically, a method is provided for manufacturing at least one wafer or chip. The method includes obtaining image data of the at least one wafer or chip. The method further includes correcting the image data to remove normal variation within the image data. The method further includes comparing the corrected image data to image data for at least one other wafer or chip to determine whether the corrected image data for the at least one wafer or chip shows a defect or anomaly beyond that of the normal variation. The method further includes placing the at least one wafer or chip into a category of fabrication based on the comparison.

Growing community of inventors

Burlington, VT, United States of America

Jared P Yanofsky