Rambus Inc.

Apple Inc.

Other

Highlands Corporation

Jared L Zerbe

Mark A Horowitz

Brian S Leibowitz

Kevin S Donnelly

Vladimir Marko Stojanovic

Bruno Werner Garlepp

Fred F Chen

Craig Edward Hampel

Alfredo Moncayo

Jihong Ren

Carl William Werner

Hae-Chang Lee

Pak Shing Chau

William Franklin Stonecypher

Qi Lin

Richard Maurice Barth

Stefanos Sidiropoulos

Anthony G Bessios

Grace Tsang

Frederick Abbott Ware

Masum Hossain

Barry William Daly

Jun Y Kim

Andrew P Ho

Jason C Wei

Brian Hing-Kit Tsang

Donald C Stark

Roxanne T Vu

Leung Yu

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

John Wood Poulton

Ramin Farjad-Rad

John M Wilson

Lei Luo

Fariborz Assaderaghi

John Cronan Eble, Iii

Amir Amirkhany

Ian P Shaeffer

Billy Wayne Garrett, Jr

Teva J Stone

Wayne D Dettloff

Andrew C C Ho

Yue Lu

Jaeha Kim

Sanjay Pant

John Eble

Jun Zhai

Kyung Suk Oh

Shawn Searles

Emerson S Fang

Hsuan-Jung Su

Ely K Tsern

Clemenz L Portmann

Paul G Davis

Abhijit Mukun Abhyankar

Andrew C Ho

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Anthony Chan Carusone

Dustin Tarl Dunwell

Brian H Tsang

Kevin M Lynch

Huy M Nguyen

Yohan Usthavia Frans

William C Athas

Thomas H Lee

Kambiz Kaviani

Elad Alon

Andreas Edgar Schobel

Haw-Jyh Liaw

Gierad Laput

Jung-Hoon Chun

Shawn R Scully

Kashinath Ullhas Prabhu

Charles Maalouf

Shiwen Zhao

Dennis Kim

Haechang Lee

Myeong-Jae Park

Scott C Best

Jade M Kizer

Wayne S Richardson

Timothy Michael Johnson

Pravin Kumar Venkatesan

Pradeep Batra

Chaofeng Huang

Yiu-Fai Chan

Binu K Mathew

Julia C Ng

Marko Aleksic

Timothy Chang

Andy Chan

Zaid M Nadeem

Andy J Zhou

Xinhao Wang

Metha Jeeradit

Brian L Leibowitz

Bryan D Raines

Anshuman Bhuyan

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

High-speed signaling systems with adaptable pre-emphasis and equalization

Individual health related events (e.g., handwashing events) can be detected based on multiple sensors including motion and audio sensors. Detecting a qualifying handwashing event can include detecting a qualifying scrubbing event based on motion data (e.g., accelerometer data) and a qualifying rinsing event based on audio data. In some examples, power consumption can be reduced by implementing one or more power saving mitigations.

Methods and apparatus for detecting individual health related events

This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Split-path equalizer and related methods, devices and systems

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Low power edge and data sampling

A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Low-power source-synchronous signaling

The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Using dynamic bursts to support frequency-agile memory interfaces

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Clock generation for timing communications with ranks of memory devices

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Multi-die fine grain integrated voltage regulation

Sensing circuitry of a first electronic device can be configured to sense a signal transmitted by the second, external electronic device contacting and coupling through the body of the user. The first electronic device can be configured to detect the contact while receiving data from the second device, and determine whether the signal transmitted by the external device corresponds an 'intentional touch,' or corresponds to a signal coupling between a different body part and the external device or through a different signal pathway (e.g., electromagnetically, through the air, etc.).

Systems, methods and apparatus for through skin communication and noise disambiguation

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Data transmission using delayed timing signals

Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Detecting power supply noise events and initiating corrective action

Growing community of inventors

Woodside, CA, United States of America

Jared L Zerbe