Intel Corporation

Jared E Bendt

Shaun M Conrad

Janardhan Lavakumar

Ravishankar Iyer

Andrew J Herdrich

Avinash N Ananthakrishnan

Ashish V Choubal

Rameshkumar G Illikkal

Jaideep Moses

Sadagopan Srinivasan

Vijay S R Degalahal

A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.

Method and apparatus for efficient store/restore of state information during a power state transition

Method and apparatus for efficient store/restore of state information during a power state

Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.

Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing

Growing community of inventors

Hillsboro, OR, United States of America

Jared E Bendt