Nan Ya Technology Corporation

Jar-Ming Ho

Yi-Nan Chen

Hsien-Wen Liu

Shian-Jyh Lin

Ming-Yuan Huang

Mao-Ying Wang

Yu-Pi Lee

Tse-Chuan Kuo

Shun-Fu Chen

The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

Semiconductor structure with air gap in pattern- dense region and method of manufacturing the same

The present disclosure provides a method for preparing a memory device. The method includes forming a first bottom cell within a bottom substrate, comprising: forming a first bottom capacitor within the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line. The method also includes forming a first top cell within a top substrate, comprising: forming a first top capacitor within the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first top channel layer surrounded by the first top word line. The method further includes forming a common bit line between the first bottom cell and the first top cell and extending along a second direction substantially perpendicular to the first direction.

Method for preparing memory device having protrusion of word line

Semiconductor structure with air gap in pattern-dense region and method of manufacturing the same

The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.

Memory device having protrusion of word line

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm/Watt and about 0.25° C. cm/Watt.

Semiconductor device with thermal release layer and method for fabricating the same

The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

Semiconductor device with carbon hard mask and method for fabricating the same

The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

Method for preparing semiconductor device with air gap in pattern-dense region

The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.

Method for fabricating semiconductor device including capacitor structure

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first pad positioned above the substrate, and a first redistribution structure including a first redistribution conductive layer positioned on the first pad and a first redistribution thermal release layer positioned on the first redistribution conductive layer. The first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04&#xb0; C. cm/Watt and about 0.25&#xb0; C. cm/Watt.

The present disclosure provides a semiconductor device with an air gap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

Semiconductor device with air gap in pattern-dense region and method for forming the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate and a first crack-detecting structure positioned in the substrate and comprising a first capacitor unit. The first capacitor unit comprises a first bottom conductive layer positioned in the substrate, a first capacitor insulating layer surrounding the first bottom conductive layer, and a first buried plate surrounding the first capacitor insulating layer.

Semiconductor device and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of landing pads disposed over the substrate, at least one of the plurality of landing pads comprising a protruding portion of a capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug; a plurality of bit line contacts disposed over the substrate and a plurality of bit lines respectively disposed over the plurality of bit line contacts. The bit line is an undulating stripe extending between two adjacent capacitor contacts; and a plurality of capacitor structures respectively disposed over the plurality of landing pads.

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor substrate, a first pillar and a second pillar over the semiconductor substrate, an isolation layer over the semiconductor substrate, and a first contact pad and a second contact pad embedded in the isolation layer. A first upper surface of the first pillar is higher than a second upper surface of the second pillar. The first pillar and the second pillar are laterally surrounded by the isolation layer. The first contact pad is disposed over the first pillar. The second contact pad is disposed over the second pillar, and a first pad width of the first contact pad is not greater than a second pad width of the second contact pad.

Semiconductor structure and method for manufacturing the same

An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

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Taipei, Taiwan

Jar-Ming Ho