Holtek Semiconductor Corp.

Jar-Lin Chen

Jen-Chung Weng

An image-clock adjusting circuit is provided and includes a phase comparator, a clock controller, and a timing generator. The phase comparator receives a power source signal and a vertical synchronous signal and compares a phase of the power source signal with that of the first vertical synchronous signal for producing at least a phase comparison signal. The clock controller receives the phase comparison signal and the vertical synchronous signal, produces a pixel clock signal and intermittently adjusts a clock width of the pixel clock signal. The timing generator receives the pixel clock signal and adjusts the vertical synchronous signal into an adjusted vertical synchronous signal being nearly in phase with the power source signal. Therefore, The effect suppressing the phenomenon of the color rolling with the simpler circuit is accomplished.

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Hsinchu, Taiwan

Jar-Lin Chen