Altera Corporation

Janusz K Balicki

Khusrow Kiani

Bezhad Nouban

Bahram Ahanin

William W Leong

John C Costello

Behzad Nouban

Ken Ming Li

Nghia Tran

Ken-Ming Li

Ying Xuan Li

A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.

System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly

System for coupling programmable logic device to external circuitry

A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

Method and apparatus for reducing the number of programmable

A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

High speed, low power macrocell

A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Programmable logic device having fast programmable logic array blocks

Macrocell comprised of two look-up tables and two flip-flops

Flexible configuration logic array block for programmable logic devices

Growing community of inventors

San Jose, CA, United States of America

Janusz K Balicki