International Business Machines Corporation

Globalfoundries U.S. Inc.

Janusz Jozef Nowak

Michael C Gaidis

Daniel Christopher Worledge

Eugene John O'Sullivan

John Kenneth DeBrosse

Anthony J Annunziata

Chung H Lam

Gen Pei Lauer

Nathan P Marchack

Jonathan Zanhong Sun

Michael F Lofaro

Yu Lu

Mark Curtis Hayes Lamorey

David William Abraham

Philip Louis Trouilloud

Bruce Bennett Doris

Pouya Hashemi

Sivananda K Kanakasabapathy

Chandrasekharan Kothandaraman

Lubomyr Taras Romankiw

Solomon Assefa

Guohan Hu

Yu Luo

Doreen D DiMilia

Philip L Trouilloud

An approach to provide a funnel-shaped spin-transfer torque (STT) magnetoresistive random-access memory (MRAM) device with a dual magnetic tunnel junction. The approach includes providing a metal pillar on a connection to a semiconductor device. The approach includes providing a first reference layer on the metal pillar and on a portion of a first interlayer dielectric adjacent to the metal pillar. The approach includes providing a first tunnel barrier on the first reference layer and a free layer on the first tunnel barrier layer. The approach includes providing a second tunnel barrier on the free layer and a second reference layer on the second tunnel barrier of the semiconductor structure of the funnel-shaped spin-transfer torque MRAM device.

Three-dimensional funnel-like spin transfer torque MRAM cell with a non-uniform thicknesses in each layer

A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, and forming a second magnetic tunnel junction stack on the spin conducting layer. The second magnetic tunnel junction stack has a width that is greater than a width of the first magnetic tunnel junction stack.

Inverted wide base double magnetic tunnel junction device

A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming a conical insulator core, forming a conductor layer on the insulator core, forming a magnetic free layer on the conductor layer, forming a barrier layer on the magnetic free layer, and forming a magnetic fixed layer on the barrier layer.

Magnetic tunnel junction having tapered all-around structure

A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized.

Annealed seed layer for magnetic random access memory

A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Combined CMP and RIE contact scheme for MRAM applications

A method of electrolessly plating an iron-based substrate, including immersing an iron-based substrate in an acidic solution, immersing the iron-based substrate in a basic complexing solution, immersing the iron-based substrate in a catalytic metal solution including a catalytic metal, and immersing the iron-based substrate in an electroless nickel plating solution or an electroless cobalt plating solution.

Pretreatment of iron-based substrates for electroless plating

Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Spin transfer torque cell for magnetic random access memory

A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

Structure and method to reduce shorting and process degradation in stt-MRAM devices

Structure and method to reduce shorting and process degradation in STT-MRAM devices

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Highland Mills, NY, United States of America

Janusz Jozef Nowak