Via Technologies, Inc.

Janq-Lih Hsieh

Jing-Rung Wang

This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing unit receives a first address signal and a second address signal from the north bridge chip, and correspondingly transmits an index signal and a test data to the north bridge chip. The comparing unit compares the first and the second address signal to generate a comparing signal. And the recording unit records the first and the second address signal and the comparing signal. The north bridge chip connects to the south bridge chip via a bus, and the debug device also connects to the south bridge chip. Therefore the north bridge chip and the debug device transmit to both through the south chip.

Growing community of inventors

Taipei, Taiwan

Janq-Lih Hsieh