Analog Devices,inc.

Stmicroelectronics N.v.

Janos Kovacs

Kevin J McCall

Ronald Kroesen

Wyn T Palmer

Steven R Robinson

Philip Eugene Quinlan

Jason D Byrne

Scott C Munroe

Jack Kenney

A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

Sampled delay locked loop insensitive to clock duty cycle

A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

Programmable pulse slimmer system for low pass ladder filter

A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.

Burst error limiting symbol detector system

A constrained fixed delay tree search receiver for an MTR=2 encoded communication channel includes a filter circuit responsive to a received signal for producing a channel impulse response including a plurality of filtered samples with at least one of the post cursor filter samples forced to zero; a feedback equalizer circuit responsive to the channel symbol identified at the output of the receiver and the filtered samples for producing corresponding truncated samples comprised of linear combinations of coefficients characterizing the channel and channel symbols constrained by the MTR=2 code; and a detector including a discrete time filter responsive to the truncated samples for generating a set of signals defining a multi-segment boundary which divides the combination of the set of signals into two groups; a comparator circuit responsive to the discrete time filter for determining to which of the groups the combination of the set of signals belongs, and a logic circuit, responsive to the comparator circuit, for determining the value of a channel symbol as a function of the group in which the set of symbols belongs.

Constrained fixed delay tree search receiver for a MTR=2 encoded

A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

Composite load circuit

A switched capacitance phase locked loop (PLL) system includes a filter circuit having a scaling channel for scaling the phase error; an integrating channel for integrating the phase error; and a summing device for combining the scaled phase error and the integrated phase error; a voltage controlled oscillator (VCO) responsive to the summing device produces an output; the VCO's gain is proportional to its output clock frequency; the integrating channel includes a switched capacitance integrating circuit for controlling the gain of the integrating channel proportional to the output clock frequency of the VCO and maintaining constant the ratio of, and scaling the product of, the unity gain frequency and the zero frequency of the phase locked loop to keep constant the damping factor and to scale the natural frequency of the phase locked loop with the output clock frequency of the VCO, respectively.

Switched capacitance phase locked loop system

A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

Read system for implementing PR4 and higher order PRML signals

A data receiving and processing channel including analog signal processing circuitry operable for receiving data in the form of an input analog signal, and modifying the input signal in accordance with selected parameters so as to generate a modified analog input signal. According to one embodiment, there is provided a charge domain signal equalizer which initially transforms the modified analog input signal into a corresponding analog charge domain signal, the equalizer performing waveform shaping of the analog charge domain signal in accordance with a predetermined signal response template; a charge domain analog-to-digital converter operable for converting the analog charge domain signal into a corresponding digital signal; and a digital signal processor operable for recovering a digital bit stream from the digital signal which is indicative of the original data. In an alternative embodiment, there is provided an analog-to-digital converter operable for converting the modified analog input signal into a corresponding digital signal; a charge signal equalizer which initially transforms the digital signal into a corresponding digital charge signal, the equalizer performing waveform shaping of the digital charge signal in accordance with a predetermined signal response template; and a charge domain digital signal processor operable for recovering a digital bit stream from the digital charge domain signal which is indicative of the original data.

Sampled data read channel utilizing charge-coupled devices

A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Dynamic phase selector phase locked loop circuit

A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

All-MOS precision differential delay line with delay a programmable

An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

Intrinsic R2R resistance ladder digital to analog converter

A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

Hybrid phase locked loop

A hybrid analog/digital automatic gain control gain recovery system includes a variable gain amplifier (VGA) for receiving a variable amplitude input signal; a first AGC loop includes an analog to digital converter (DAC) for receiving the analog input signal and converting it to a digital signal; a digital gain error detection circuit for detecting variations of the digital signal in a first range and generating a digital error correction signal; and a digital to analog converter (DAC) for converting the digital error correction signal to a first analog correction signal; a second analog AGC loop includes an analog gain error detection circuit, responsive to variations in the output of the VGA in a second range greater than the first range for generating a second analog correction signal; and an integrator circuit responsive to the first and second analog correction signals for providing to the VGA a control signal to adjust the gain of the VGA to accommodate variations in the input signal amplitude.

Hybrid analog digital automatic gain control gain recovery system

A center frequency controlled phase locked loop system includes a primary phase locked loop having a first voltage controlled oscillator including a first voltage to current converter whose output current drives a first current controlled oscillator to produce the primary clock signal to be locked onto an input signal; a second phase locked loop having a second voltage controlled oscillator including a second voltage to current converter whose output current drives a second current controlled oscillator to produce the synthesized clock signal whose frequency is approximately that of the input signal or integral multiple thereof; and a current copier circuit for copying the output current from the second voltage to current converter and delivering it to the first current controlled oscillator to maintain the center frequency of the first voltage controlled oscillator at approximately the output frequency of the synthesized clock signal.

Center frequency controlled phase locked loop system

A maximum likelihood detector for a continuous time disk drive read channel includes a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; this includes comparing the input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to the binary gating signals, to the input signal, and to the peak detector circuit which identifies qualified input signal peaks; and a threshold update circuit responsive to the identification of qualified input signal peaks, which adjusts the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

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North Andover, MA, United States of America

Janos Kovacs