Motorola Corporation

Freescale Semiconductor,inc.

Nxp B.v.

National Semiconductor Corporation

Sematech, Inc.

Intel Corporation

Stmicroelectronics S.r.l.

Digital Equipment Corporation

Stmicroelectronics (crolles 2) Sas

Amd Inc.

At&t Gis

Janos Farkas

Srdjan Kordic

Melissa Freeman

Kathleen C Yu

David K Watts

Rajeev Bajaj

Suresh Venkatesan

Venkat Kolagunta

Mohammed Rabiul Islam

Sebastien Petitdidier

Rajesh Tiwari

Brian George Anthony

Sanjit K Das

John Mendonca

Abbas Guvenilir

Hector Adrian Sanchez

Rahul Jairath

Nigel Graeme Cave

Yeong-Jyh Tom Lii

Kirk J Strozewski

Cindy Goldberg

Jaime A Saravia

Jason Gomez

Chelsea Dang

Maria Luisa Calvo-Munoz

Sung C Kim

John C Flake

Kevin Cooper

Yuri Solomentsev

James M Mullins

Lynne M Michaelson

George R Meyer

Sing-Mo H Tzeng

Kevin E Cooper

Jan Van Hassel

James J Murphy

Silvio Del Monaco

Lucia C Markert

Matt Stell

Jennifer Lynn Cooper

Lance B Cook

Johannes Friedrich Groschopf

Philippe Monnoyer

Farid Sebaai

Sébastien Petitdidier

Jan Van-Hassel

Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers (). A web of cleaning material () is interposed between each roller and the substrate. Various different webs of cleaning material may be used, e.g. a length of tissue, a continuous loop of cleaning material whose surface is reconditioned on each cleaning pass, adhesive material provided on a carrier tape, etc.

Apparatus for cleaning of circuit substrates

The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapor of &#x3b2;-diketone or a &#x3b2;-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method.

Surface treatment in semiconductor manufacturing

A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterized in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alkylthiol, sulfonate, methanosulfonate, and cyanide, and salts thereof. 

Capping layer formation onto a dual damescene interconnect

A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value.

Method for testing a slurry used to form a semiconductor device

A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereor, and material for coupling a dielectric layer and a metal layer in a semiconductor device

A cleaning solution for a semiconductor wafer comprises ammonia, hydrogen peroxide, a complexing agent and a block copolymer surfactant diluted in water. The cleaning solution can be used in single wafer cleaning tools to remove both particulate contaminants and metallic residues.

Cleaning solution for a semiconductor wafer

A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.

System and method for removing particles from a polishing pad

A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and passivating coupling material comprising multiple organic components for use in a semiconductor device

Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and material for coupling a dielectric layer and a metal layer in a semiconductor device

A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.

Treatment solution and method of applying a passivating layer

This disclosure describes a low particle concentration formulation for slurry which is particularly useful in continuous CMP polishing of copper layers during semiconductor wafer manufacture. The slurry is characterized by particle concentrations generally less than 2 wt %, and advantageously less than 1 wt %. In particular embodiments, where the particle concentration is in a range of 50 to 450 PPM, an 8-fold increase in polishing rate over reactive liquid slurries has been realized. Slurries thus formulated also achieve a reduction in defectivity and in the variations in planarity from wafer to wafer during manufacture, by improving the stability of polishing quality. The slurry formulations permit substantial cost savings over traditional 2-component, reactive liquid and fixed/bonded abrasive slurries. In addition the formulations provides an advantageous way during CMP to easily change the selectivity or rate of removal of one film material vs. another. Yet another use is to provide slurry 'pulsing' as a means to activate bonded abrasive or fixed abrasive slurry technology.

CMP metal polishing slurry and process with reduced solids concentration

A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Semiconductor device having a multiple thickness interconnect

Method for forming a semiconductor interconnect with multiple thickness

A copper interconnect polishing process begins by polishing ( ) a bulk thickness of copper ( ) using a first platen. A second platen is then used to remove ( ) a thin remaining interfacial copper layer to expose a barrier film ( ). Computer control ( ) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed ( ) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier ( ) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations ( ). A scrubbing operation ( ) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

Growing community of inventors

Saint Ismier, France

Janos Farkas