Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Samsung Electronics Co., Ltd.

Hewlett Packard Enterprise Development LP

Other

Janice H Nickel

Manoj K Bhattacharyya

Thomas C Anthony

Manish Sharma

Lung T Tran

Jianhua Yang

Gilberto Medeiros Ribeiro

James A Brug

Frederick A Perner

Andrew L Van Brocklin

Matthew D Pickett

Robert G Walmsley

Hans S Cho

Manuj Bhattacharyya

Richard Stanley Williams

Ning Ge

Michael Renne Ty Tan

Alexandre M Bratkovski

Zhiyong Li

Warren Bruce Jackson

John Paul Strachan

Philip John Kuekes

Wei Guang Wu

Peter James Fricke

Peter George Hartwell

Patricia A Beck

Orlando E Ruiz

Bryan H Nickel

Jinwon Park

Choi Hyejung

Moonsig Joo

Shufend Zhang

Jiwon Moon

Changgoo Lee

Yongsun Sohn

Jeongtae Kim

Jaesung Roh

A transit system includes a road, a plurality of pavement markers spaced apart along a lane line of the road, and a plurality of RF devices carried by the pavement markers. The RF devices are configured to transmit RF navigation signals to motor vehicles traveling along the road.

Navigation infrastructure for motor vehicles

An autonomous road vehicle includes means for receiving wireless identification signals during vehicle navigation and using the wireless identification signals to determine position and identification of nearby road objects. The autonomous road vehicle further includes an autonomous vehicle control system responsive to the positions and the identifications.

Object identification for autonomous road vehicles

Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.

Non-volatile resistive memory cells

A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Memory controllers

A memory device and method for altering a performance characteristic of a memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. The memory device may include a memory controller and a memory array, which may include memristive memory elements. To alter a performance characteristic, for example, the memristive memory elements may be written at sub-full resistive states which have a smaller difference between high and low resistive states, and/or the memory controller may disable a subset of memory elements and/or memory cells along a bit line and/or word line of the memory array. The subset of memory elements may be re-enable in response to the demand for bandwidth falling below the threshold, and data may be moved and/or rearranged within the memory device when the subset of memory elements is re-enabled. Altering the performance characteristic may increase a rate at which the memory device writes data.

Memory device and method for altering performance characteristic based on bandwidth demand

Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area.

Memristors having at least one junction

The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor.

Select device for cross point memory structures

A multilayer crossbar memory array includes a number of layers. Each layer includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers is a bottom set of parallel lines for an adjacent one of the layers.

Multilayer memory array

A switching device has a bottom conductor, a top conductor, and a device body formed between the top and bottom conductors. The device body has a switching layer that is switchable by means of current passed through the device body and between the top and bottom conductors. A lower via connects the bottom conductor to the device body. The width of the lower via is smaller than a width of the device body.

Structure of a switching device in an array

Memristors and their fabrication are provided. A first dielectric layer is formed over one or more conductive pathways. Vias are formed in the dielectric layer and filled with conductive material. A second dielectric layer is formed there over, and vias are formed aligned with and extending to the filled vias. A reactant fluid is introduced into the vias such that a reacted portion of the conductive material is defined within the filled vias. The vias in the second dielectric layer are then filled with conductive material such that memristors are defined. Conductive pathways are then formed over and in contact with the memristors such that each is individually addressable.

Memristors and methods of fabrication

A nanoscale switching device comprises a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region containing a switching material; an area within the active region that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array and method of forming the nanoscale switching device are also disclosed.

Nanoscale switching device

A programmable crossbar array includes a layer of row conductors and a layer of column conductors with the row conductors crossing over the column conductors to form junctions. Programmable crosspoint devices are sandwiched between a row conductor and a column conductor at a junction. Each programmable crosspoint device includes a data element with a first programming threshold and a control element with a second programming threshold, in which the second programming threshold is greater than the first programming threshold. A method for mitigating shorts in a programmable crossbar array is also provided.

Mitigation of inoperable low resistance elements in programable crossbar arrays

A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.

Memristor with embedded switching layer

A memory array with graded resistance lines includes a first set of lines intersecting a second set of lines. A line from one of the sets of lines includes a graded resistance along a length of the line.

Memory array with graded resistance lines

The present invention includes a method and system for processing images captured with an image-capturing device. According to the present invention, a method and system includes reconfiguring a display of an image based on the orientation of the image-capturing device when the image is captured. Through the use of the method and system in accordance with the present invention, a user can view captured images without having to account for a rotation of the image-capturing device. The method and system includes capturing the image with an image-capturing device, determining an orientation of the image-capturing device and reconfiguring a display of the image based on the orientation of the image-capturing device.

Growing community of inventors

Sunnyvale, CA, United States of America

Janice H Nickel