Nokia Corporation

Memory Technologies LLC

Jani Klint

Matti Kalevi Floman

Jukka-Pekka Vihmalo

Sakari Sippola

Tapio Hill

Kimmo Kalervo Kuusilinna

Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Method, an interface for volatile and non-volatile memory devices as well as a related computer program product, and a device

The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.

Thermal sensors for stacked dies

Memory interface for volatile and non-volatile memory devices

The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Memory with single and dual mode access

An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n&#x2267;2.

Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal

A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Memory bus checking procedure

A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides&#x2014;dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Addressing data within dynamic random access memory

A memory circuit () comprises at least a non-volatile random access memory () and a random access memory (). The memory circuit () also comprises a memory controller () connected by a first bus () to the non-volatile random access memory () and by a second bus () to the random access memory (). Thus, data can be transmitted between non-volatile random access memory () and random access memory () via the memory controller (). The memory circuit comprises a control bus () connected to the memory controller () to control operation of the memory circuit (). The invention also relates to a corresponding system and corresponding electronic device () in which the memory circuit () is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory () and a random access memory () are used.

Growing community of inventors

Tampere, Finland

Jani Klint