Seoul National University

Jangsaeng Kim

Jong-Ho Lee

Soochang Lee

Young-tak Seo

Seongbin Oh

Dongseok Kwon

Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a body electrode disposed on a substrate in a vertical direction; a plurality of first insulating layers and third oxide layers alternately stacked on the outer circumferential surface of the body electrode; a plurality of semiconductor bodies disposed on an outer circumferential surface of the third oxide layer; a plurality of sources alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a first side surface of the body electrode; a plurality of drains alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a second side surface of the body electrode; a plurality of word lines alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a third side surface of the body electrode; and an insulator stack positioned between the word line and the semiconductor body. The semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device, or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.

3D synapse device stack, 3D stackable synapse array using the 3D synapse device stacks and method of fabricating the stack

Provided is a 3D capacitor stack and a method for manufacturing the same. The 3D capacitor stack comprises: a drain line electrode having a pillar shape provided in a vertical direction on a substrate surface; a plurality of first insulating layers positioned in first region of an outer circumferential surface of the drain line electrode; a plurality of drains positioned in second regions of an outer circumferential surface of the drain line electrode; a plurality of insulator stacks positioned on side surfaces of the drains; and a plurality of word lines positioned on side surfaces of the insulator stacks. The word lines surrounded by the insulator stacks are positioned on the side of the drains, first insulating layers and drains are alternately stacked on the outer circumferential surface of the drain line electrode, and the word lines surrounded by the insulator stacks and the first insulating layers are alternately stacked; the drain, the word line and the insulator stack constitute a capacitor device, and the capacitor devices electrically isolated from each other by the first insulating layers are vertically stacked to form a stack structure.

3D capacitor stack and method of fabricating the stack

A neuromorphic system enabling on-chip training includes: synapse arrays where synapse devices are arranged in a cross-bar shape; a final neuron layer including a forward neuron and a backward neuron and connected to an output terminal of a last synapse array; neuron layers including a forward neuron, a backward neuron, and a memory storing signals used during a weighted value update operation of a neural network and arranged between the remaining synapse arrays except for a first and last synapse arrays; and an error calculation circuit detecting and outputting an error value of a target signal and an output signal of the forward neuron of the final neuron layer. Conductances of the synapse devices represent weighted values of the neural network and are changed by the weighted value update operation. Each synapse device is configured with a flash device, and the neuron layers are implemented with ultra-miniature devices.

Growing community of inventors

Seoul, South Korea

Jangsaeng Kim