Beijing Eswin Computing Technology Co., Ltd.

Hefei Eswin Computing Technology Co., Ltd.

Hefei Eswin Ic Technology Co., Ltd.

Hefel Eswin Computing Technology Co., Ltd.

Jangjin Nam

Dongmyung Lee

Donghoon Baek

Daejoon Lee

Sangmin Park

Zhengbei Hua

Hao Fan

Jiajhang Wu

Dongsoo Park

Minsung Kim

Long Zhong

Enwei Ni

The voltage regulator comprises: a voltage regulation circuit, a detection circuit and at least one current source unit. An output terminal of the voltage regulation circuit is electrically connected to a first terminal of each of the current source units, and is configured to be electrically connected to a load; and a second terminal of each of the current source units is electrically connected to a first voltage terminal. The detection circuit is electrically connected to the voltage regulation circuit, and is configured to: when the voltage regulation circuit is in a light-load state, control a designed number of the current source units to connect to the output terminal of the voltage regulation circuit to output designed current, and when the voltage regulation circuit is in a heavy-load state, control each of the current source units to disconnect from the output terminal of the voltage regulation circuit.

Voltage regulator, power supply system and receiver

The present application provides a method for controlling an offset voltage in a display device, a display device and a storage medium. The method for controlling an offset voltage in a display device comprises: generating a chopper signal based on at least one of a data output control signal and a polarity inversion control signal; and, controlling, according the chopper signal, the polarity of an offset voltage of an operational amplifier in the display device, so that the offset voltage is equivalently eliminated within at least one of a design space range and a design time range. By using the control method of the present application, without using large-size transistors and providing more signals, the display effect can be ensured and the size of the chip can also be reduced.

Method for controlling offset voltage in display device, display device, and storage medium

The present disclosure provides a receiver circuit and a receiver circuit control method. In the present disclosure, the input data is detected by a detection circuit to obtain a data rate detection result, and the bandwidth of the receiver is automatically adjusted according to the data rate detection result.

Receiver circuit and receiver circuit control method

A method, a detection circuit and an electronic device for detecting timing sequence of serializer are provided. The method for detecting a timing sequence of a serializer includes: sampling serial data to obtain first sampled serial data and second sampled serial data, wherein the serial data is obtained by parallel-serial conversion of parallel data used for detection by the serializer, and the first sampled serial data and the second sampled serial data respectively include values corresponding to different data bits of the serial data; performing logical operation between on the first sampled serial data and the second sampled serial data to obtain a first result signal; and performing timing sequence detection on the first result signal, wherein the timing sequence detection is used for detecting whether the timing sequence correctness of the serializer is correct.

Method, detection circuit and electronic device for detecting timing sequence of serializer

Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain.

Method and system for transmitting data, timing controller, and source driver chip

Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Timing controller, source driver chip, drive circuit, and drive control method

A control method for a data driver, a control method for a timing controller, a data driver control apparatus, a timing controller, an electronic device, and a storage medium are provided. The control method for the data driver includes: obtaining a data comparison signal, where the data comparison signal represents a comparison relationship between first display data for enabling a first pixel row to display and second display data for enabling a second pixel row to display, and in time, the second pixel row is driven to display after the first pixel row is driven to display; and controlling an operation state of the data driver according to the data comparison signal.

Control method for data driver and timing controller, and electronic device

Provided is a data transmission method, including: sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration; sending first configuration information to the source driver chip over a data channel in response to completing the clock calibration by the source driver chip, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

Data transmission method, timing controller, and storage medium

Provided is a data transmission method in a timing controller. The data transmission method includes sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform a clock calibration; successively sending, in response to completing the clock calibration by the source driver chip, a first identification code and an initialization control instruction to the source driver chip over a data channel, wherein the first identification code indicates a start of transmission of the initialization control instruction, and the initialization control instruction comprises configuration information, the configuration information instructing the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

This disclosure provides a voltage controlled oscillator and a control method thereof, a P2P interface circuit, an electronic device, and relates to the field of voltage controlled oscillation technology. The voltage controlled oscillator includes N stages of delay units, and the delay unit of each stage includes: a first inverter, a second inverter, a third inverter, and a fourth inverter; both the second inverter and the third inverter are electrically connected to a frequency control terminal, and whether to activate the second inverter and the third inverter is controlled by the frequency control terminal.

Voltage controlled oscillator and control method thereof, P2P interface circuit, electronic device

A slew rate boosting circuit, a source driver chip and a display device are provided in the present disclosure. The slew rate boosting circuit comprises: a first latch configured to receive and store first data; a second latch configured to receive and store second data, the second data being next to the first data; a first level shifter; an amplifier; and a slew rate boosting module configured to receive a high voltage data signal as current input data, and adjust a slew rate of an output stage of the amplifier according to a value of a specified bit of the first data, a value of a specified bit of the second data and the current input data.

Slew rate boosting circuit, source driver chip and display device

The present disclosure provides a pre-emphasis circuit, method and display device, and belongs to a field of display driving. The pre-emphasis circuit according to the disclosure can determine whether to output a pre-emphasis voltage corresponding to grayscale of current input data via an input terminal of an amplifier according to data input to a data terminal by adding an amplifier input pre-emphasis module. Rapid conversion of output voltage can be realized without increasing the quiescent current of the amplifier, while the stability of temperature of the IC is ensured.

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Beijing, China

Jangjin Nam