Sk Enpulse Co., Ltd.

Skc Solmics Co., Ltd.

Samsung Electronics Co., Ltd.

Korea Research Institute of Chemical Technology

Nhn Corporation

Skc Co., Ltd.

Hewlett-Packard Development Company, L.p.

Ulsan National Institute of Science and Technology

Jang Won Seo

Hye Young Heo

Jong Wook Yun

Sunghoon Yun

Jaein Ahn

Eun Sun Joeng

Jae In Ahn

Jun Hong Noh

Nam Joong Jeon

Kyung Hwan Kim

Sang Il Seok

Su Young Moon

Joonsung Ryou

Sungwon Kim

Hyuk Hee Han

Tae Youl Yang

Myung Kwan Choi

Beom Seok Seo

Se Jin Cheon

Tae Kyoung Kwon

Sung Hoon Yun

Jung Hoon Lee

Ji Young Lee

Yong Hwan Kwon

Myung-Ok Kyun

Jaemin Lee

Jean-Christophe Naour

Yoo Jin Choi

Takuya Ito

Seung Beom Yang

Eun Jung Jeon

Whan Woo Lee

Soo Hyun Kim

Yong-Jae Kwak

Sung Hyun Yoon

Koo Won Park

Seung Rae Kim

Young Pil Kwon

Hye Jin Na

Tae Hyeon Park

Kang Sik Myung

Jae Hoon Lee

Hee Jeong Bae

Woo Seok Hwang

Woo-seok Hwang

Joon Ho Lee

Min Hyung Kim

Chang Soo Lee

Joosun Moon

Young Kwan Kim

Jongmin Shim

Junghwan Shin

PillKyoung Moon

Young Chan Kim

Jung Nam Lee

Sang-Il Seok

Yong Jae Kwak

Tae Hwan Park

Hyeyoung Heo

Yong Ju Jeong

Kang Sik F Myung

Wook Seok Yang

Jae Gu Lee

Eui Hyuk Jung

Seong Sik Shin

Ju Hyun Seong

Seung Kyun Kim

Provided is a polishing pad including a polishing layer, wherein the nuclear magnetic resonance (NMR)C spectrum of a processed composition prepared by adding 1 g of the polishing layer to a 0.3 M aqueous solution of potassium hydroxide (KOH) and allowing the mixture to react in a closed container at a temperature of 150° C. for 48 hours includes a first peak appearing at 15 ppm to 18 ppm, a second peak appearing at 9 ppm to 11 ppm, a third peak appearing at 138 ppm to 143 ppm, and a fourth peak appearing at 55 ppm to 65 ppm, and the softening control index calculated by Equation 1 is 0.10 to 0.45. The polishing pad includes the polishing layer having physical properties corresponding to the softening control index, and thus may exhibit a removal rate and defect prevention performance within desired ranges in polishing of a polishing target.

Polishing pad and method of fabricating semiconductor device using the same

The present disclosure relates to an endpoint detection window of a polishing pad for use in a polishing process. The polishing pad may prevent an error in detection of the endpoint of the polishing process by preventing a difference in endpoint detection performance from occurring due to a difference in the wavelength of a laser between polishing apparatuses. The present disclosure may also provide a method of fabricating a semiconductor device using the polishing pad.

The present disclosure relates to a polishing pad, a method of manufacturing the polishing pad, and a method of manufacturing a semiconductor device using the same. In the polishing pad, an unexpanded solid-phase blowing agent is included in a polishing composition when a polishing layer is manufactured, and the unexpanded solid-phase blowing agent is expanded during a curing process to form a plurality of uniform pores in the polishing layer, such that defects occurring on a surface of the semiconductor substrate may be prevented. In addition, the present disclosure may provide a method of manufacturing a semiconductor device to which the polishing pad is applied.

Polishing pad, manufacturing method thereof and preparing method of semiconductor device using the same

A polishing pad sheet which provides optimized interfacial properties for the laminated structure of a polishing pad based on appropriate elasticity and high durability, and in which the polishing pad having the polishing pad sheet applied thereto not only has its intrinsic function such as the polishing rate or the like, but also is capable of realizing the function without damage even during the polishing process in a wet environment for a long time, and a polishing pad to which the polishing pad sheet is applied. The polishing pad sheet includes: a first surface which is a polishing layer attachment surface; and a second surface which is a rear surface of the first surface, wherein the first surface has a value of the following Equation 1 of 4.20 to 5.50:4.20≤(|Sv|)/Sz×P (%)≤5.50.

Polishing pad sheet, polishing pad, and method for manufacturing semiconductor device

The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

Polishing pad, preparation method thereof and method for preparing semiconductor device using same

The composition according to an embodiment employs a mixture of curing agents, which comprises a first curing agent containing sulfur and a second curing agent containing an ester group, whereby it is possible to control the physical properties of the polishing pad as necessary.

Composition for polishing pad and polishing pad

The present invention provides a polishing pad whose crosslinking density is adjusted to enhance the performance of the CMP process such as polishing rate and cut pad rate. In addition, in the process for preparing a polishing pad according to the embodiment, it is possible to implement such a crosslinking density by a simple method of controlling the preheating temperature of the mold for curing. Thus, the polishing pad may be applied to a process of preparing a semiconductor device, which comprises a CMP process, to provide a semiconductor device such as a wafer of excellent quality.

Polishing pad with improved crosslinking density and process for preparing the same

The present disclosure relates to a polishing system in which accuracy and easiness of attachment and detachment of a polishing pad to a surface plate are maximized, the polishing system including: a surface plate having a polishing pad mounted on an upper portion; and the polishing pad mounted on the surface plate, in which the polishing pad includes: a polishing surface and a surface plate attachment surface that is a rear surface of the polishing surface, the surface plate attachment surface includes: at least one engraved portion, the surface plate includes at least one embossed portion, and the embossed portion and the engraved portion have a complementary coupling structure, and a method of manufacturing a semiconductor device to which the polishing system is applied.

Polishing system, polishing pad and method of manufacturing semiconductor device

Embodiments relate to a polishing pad, which comprises a window having a hardness similar to that of its polishing layer. Since the polishing pad comprises a window having a hardness and a polishing rate similar to those of its polishing layer, it can produce an effect of preventing scratches on a wafer during a CMP process. In addition, the polishing layer and the window of the polishing pad have a similar rate of change in hardness with respect to temperature, so that they can maintain a similar hardness despite a change in temperature during the CMP process.

Polishing pad comprising window similar in hardness to polishing layer

The present disclosure provides a polishing pad, which may maintain polishing performances required for a polishing process, such as a removal rate and a polishing profile, minimize defects that may occur on a wafer during the polishing process, and polish layers of different materials so as to have the same level of flatness even when the layers are polished at the same time, and a method for producing the polishing pad. In addition, according to the present disclosure, it is possible to determine a polishing pad, which shows an optimal removal rate selectivity along with excellent performance in a CMP process, through the physical property values of the polishing pad without a direct polishing test.

Polishing pad, method for producing the same and method of fabricating semiconductor device using the same

Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Polishing pad, process for preparing the same, and process for preparing a semiconductor device using the same

Disclosed is a method for producing a polishing pad, the method comprising the steps of: providing a polishing layer; forming a first through-hole penetrating the polishing layer; providing a support layer facing the polishing layer; interposing an adhesive layer between the polishing layer, which has the first through-hole, and support layer, and adhering the polishing layer and support layer to each other by means of the adhesive layer; forming, with the first through-hole as a reference point, a third through-hole penetrating the adhesive layer on a set area thereof, and a second through-hole penetrating the support layer on a set area thereof; and inserting a window inside the first through-hole.

Polishing pad and method for producing same

Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Porous polishing pad and process for producing the same all fees

Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Porous polyurethane polishing pad and process for producing the same

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Busan, South Korea

Jang Won Seo