Skhynix Inc.

Hynix Semiconductor Inc.

Jang Uk Lee

Kang Sik Choi

Suk Ki Kim

Sung Cheoul Kim

Mi Ra Choi

Hae Chan Park

Ja Chun Ku

Jin Hyock Kim

A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.

Methods of fabricating transistors with a protection layer to improve the insulation between a gate electrode and a junction region

A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof

A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

High-integration semiconductor memory device and method of manufacturing the same

A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Phase change memory apparatus and fabrication method thereof

Semiconductor memory device having dummy conductive patterns on interconnection

A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.

Method of fabricating phase change memory device capable of reducing disturbance

A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

Phase change memory device having an improved word line resistance, and methods of making same

A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.

Method of manufacturing a phase change memory device using a cross patterning technique

Phase change memory device capable of reducing disturbance

A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Growing community of inventors

Gyeonggi-do, South Korea

Jang Uk Lee