Samsung Electronics Co., Ltd.

Jang-seok Choi

Hoe-Ju Chung

Uk-Song Kang

Hoon Shung Lee

Yong-Hoon Kang

Beom-Sig Cho

A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling command, the filling command determiner connects a first source voltage to a bitline and connects a second source voltage to a complementary bitline corresponding to the bitline. The bitline is connected to a selected memory cell corresponding to the address signal.

Semiconductor memory device and semiconductor memory system

In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state. As a result, the operating speed and reliability of the system including the memory device may be improved.

Method of optimizing data training in system including memory devices

A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Growing community of inventors

Seoul, South Korea

Jang-seok Choi