Skhynix Inc.

Jang-Ryul Kim

Hyuk Soo Lee

Hoiju Chung

Young-Do Hur

Young-Jun Ku

Jong-Chern Lee

Dae-Suk Kim

A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.

Memory device detecting an error in write data during a write operation, memory system including the same, and operating method of memory system

A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.

Memory system and operating method thereof

A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code based on write data, and generate a second system error correction code based on the write data and the first system error correction code; and a memory including: a memory error correction code generation circuit configured to generate a memory error correction code based on the write data and the first system error correction code transferred from the memory controller; and a memory core configured to store the write data, the first system error correction code, the second system error correction code and the memory error correction code.

A memory device includes: an in-memory error correction code generating circuit suitable for generating an in-memory error correction code based on a data received from a memory controller during a write operation; a memory core suitable for storing the received data and the in-memory error correction code during the write operation; an in-memory error correction circuit suitable for correcting an error of the data which is read from the memory core based on the in-memory error correction code which is read from the memory core during a read operation; and a data transmitter suitable for transferring the data whose error is corrected by the in-memory error correction circuit to the memory controller during the read operation, and transferring the data which is read from the memory core to the memory controller during a read retry operation.

Memory device, memory system including the same and operation method of the memory system

A memory system includes an error correction code ('ECC') generation circuit using write data to generate an ECC to be stored together with the write data; a memory device, during a write operation, storing received data and a received ECC in a memory core, and, during a read operation, checking for an error in data read from the memory core, correcting the error in read data using the ECC and outputting error-corrected data and the ECC, when the error in the read data is between one bit and N bits inclusive, and outputting the read data and the ECC when no error is present in the read data or the error in the read data exceeds N bits; and an error correction circuit correcting, when an error is present in data outputted from the memory device, the error in the data outputted using an ECC outputted from the memory device.

Memory device selectively correcting an error in data during a read operation, memory system including the same, and operating method of memory system

A semiconductor device includes: first to Ninput terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kinput terminal (where K is an integer ranging from 1 to N&#x2212;1) is defective among the first to Ninput terminals, (K+1)to Ninput terminals receive signals of Kto (N&#x2212;1)input terminals, respectively, and the redundant input terminal receives a signal of the Ninput terminal.

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Gyeonggi-do, South Korea

Jang-Ryul Kim