Electronics and Telecommunications Research Institute

Jang Hong Yoon

Dong Soo Kim

Young Soo Kim

Jeong-Seok Lim

Jung-Gil Park

Tae Youl Yang

Young Ho Son

CheolYong Park

Dae Seon Park

Tae Uk Yang

Seong Jun Shin

Seung Soo Lee

An apparatus includes a user input unit, a display unit, a control unit, and a buffer unit. The display unit includes a speed setting menu. The control unit selects a mode from the speed setting menu in response to the selection signal of the user, and controls a compression ratio of a voice codec and a transfer rate of a modem corresponding to a transmission-side radio, and a reception rate of a modem and a restoration rate of a voice codec corresponding to a reception-side radio, based on the selected mode. The buffer unit performs a storage function if there is a difference between the compression ratio of the voice codec and the transfer rate of the modem or if there is a difference between the reception rate of the modem and the restoration rate of the voice codec.

Apparatus and method for improving communication quality of radio

Provided is a method and apparatus for compressing a text and an image. When compressing the text and image, it is possible to group valid lines with data into each line having a common element, and compress and encode the data of the valid lines. Accordingly, it is possible to reduce a data loss that may occur in a tactical communication environment with a poor channel state due to a bit sleep or a burst error. In the case of the text, it is possible to perform lossless compression on only a valid line with data and thereby improve compression efficiency. In the case of the image, it is possible to perform loss compression on valid lines, and then restore the partially damaged data using an ECC even when data is partially damaged. Accordingly, it is possible to improve compression efficiency and the entire data transmission success rate.

Method and apparatus for compressing text and image

A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal; and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter.

Shrinking key generator for parallel process

Growing community of inventors

Daejeon, South Korea

Jang Hong Yoon