Electronics and Telecommunications Research Institute

Jang Hong Choi

Hyun Kyu Yu

Kyung Hwan Park

Bon Tae Koo

Ik Soo Eo

Seong Do Kim

Hyun Ho Boo

Cheon Soo Kim

Min Woo Park

Mi Jeong Park

Seon-Ho Han

Pil Jae Park

Seon Ho Han

Dong Woo Kang

Min Sang Park

Mun Yang Park

Ja Yol Lee

Song Cheol Hong

Sang-Kyun Kim

Kisu Kim

Sun Bo Shim

Jae Hong Jang

Disclosed is a radar device capable of operating in a dual mode, which includes a transmitter that includes a first signal generator that generates a Doppler radar signal and a second signal generator that generates a Frequency Modulated Continuous Wave (FMCW) radar signal, a receiver that receives a reflected signal reflected from a target and converts the reflected signal to a digital signal, a signal processing circuit that processes the digital signal differently depending on the dual mode to output an output signal, a signal analysis circuit that analyzes the output signal, and a controller that controls operations of the transmitter, the receiver, the signal processing circuit, and the signal analysis circuit, and the dual mode includes a first mode in which the first signal generator is activated and a second mode in which the second signal generator is activated.

Radar device operating in dual mode and operation method thereof

Provided is a drive amplifier. A drive amplifier may include: a main circuit configured to receive an RF input signal and output a first RF output signal; and a selective bias adjustment circuit comprising a first common gate transistor to which a first common gate bias voltage is applied and a second common gate transistor to which a second common gate bias voltage is applied, and configured to output a second RF output signal using the first common gate transistor and the second common gate transistor.

Drive amplifier

Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.

Phase demodulator with negative feedback loop

Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.

Transmitter for carrier aggregation

A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.

Method and device for calibrating IQ imbalance and DC offset of RF tranceiver

Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.

Interpolation filter based on time assignment algorithm

The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.

Single frequency synthesizer based FDD transceiver

A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

Digital RF converter, digital RF modulator and transmitter including the same

Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.

Digital analog converter and method for calibrating sources thereof

An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Time-to-digital converter and all digital phase-locked loop including the same

Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.

Digital RF converter and RF converting method thereof

Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.

Apparatus for automatic gain control and wireless receiver employing the same

There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table.

Apparatus for linearization of digitally controlled oscillator

The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

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Daejeon, South Korea

Jang Hong Choi