Samsung Electronics Co., Ltd.

Jang-Ho Cho

Hee-Seok Lee

Yong-hoon Kim

Hyo-Soon Kang

A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Semiconductor chip and a semiconductor package having a package on package (POP) structure including the semiconductor chip

A simultaneous multithreading processor determines, for each thread, the processing time occupied by each thread in the processing pipeline of the processor. Based on the determined processing times, a fetch unit in the processing pipeline determines the thread from which to fetch the next instruction.

Thread selection for fetching instructions for pipeline multi-threaded processor

A branch predictor outputs either a predicted conditional branch or an inverted predicted conditional branch as a final branch prediction outcome, in response to a predicted accuracy history signal based on one or more accuracy history bits. According to the accuracy history bit, it is determined whether the branch prediction outcome of the branch predictor is correct. If the predicted conditional branch is correct, the branch predictor outputs the predicted conditional branch, and if the predicted conditional branch is not correct, the branch predictor outputs the inverted predicted conditional branch, in response to the predicted accuracy history signal. For performing this process, the branch prediction appends an accuracy history table and a multiplexer to a conventional branch predictor, so that the branch prediction according to the present invention can reduce the misprediction with relatively simple circuitry and low hardware cost.

Growing community of inventors

Yongin-si, South Korea

Jang-Ho Cho