National Semiconductor Corporation

Samsung Electronics Co., Ltd.

Texas Instruments Corporation

Jang Dae Kim

Jacek J Marcinkowski

Steve A Martinez

Rajesh R Berigei

Satya N Mishra

Hui X Li

Alan P Bucholz

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to determine if an input address falls within a first address range mapped to the first memory macro, in response to determining that the input address falls within the first address range mapped to the first memory macro, access the first memory macro with an address on an address bus of the first memory macro mapped from the input address, and in response to determining that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set the address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

System and method of address mapping for saving memory macro address bus toggle power

System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

System and method for balancing electrical energy storage devices via differential power bus and capacitive load switched-mode power supply

System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and capacitive load switched-mode power supplies. The switched-mode power supplies transfer the electrical energy between the load capacitors and the differential power buses to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

A dipole oscillation tank circuit includes a first capacitive structure, an inductive structure, and a second capacitive structure connected in series. The tank circuit transfers electric energy back and forth between the capacitive structures in dipole oscillation cycles. A renewal circuit injects energy into the tank circuit to replenish energy lost during the oscillation cycles. A switch is connected in parallel across the first capacitive structure and in parallel across the inductive structure and the second capacitive structure. During one phase of the oscillation cycles, the switch is opened for current to flow through the first capacitive structure and the inductive structure, and then closed to bypass the first capacitive structure. During another phase of the oscillation cycles, the switch is closed to bypass the first capacitive structure and then opened for current to flow through the first capacitive structure and the inductive structure.

Energy-conserving driver for reactive loads

An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a 'golden' reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs. The cost surface modeling with a Latin Hypercube Sampling design-of-experiment provides a statistical mathematical approximation of the actual design's error cost surface, speeding up the optimization by replacing the costly simulation of the actual design with mere evaluation of the mathematical cost surface model expression.

Simultaneous optimization of analog design parameters using a cost function of responses

An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

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San Jose, CA, United States of America

Jang Dae Kim