Lam Research Corporation

North American Philips Corp, Signetics Division

Janet M Flanner

Ian J Morey

Linda N Marquez

Susan Ellingboe

Joel M Cook

John Lang

Prashant Gadgil

Adrian Doe

Christine M Janowiak

Robert P Chebi

James C Vetter

Michelangelo Delfino

Paulus Z Van Der Putte

Ting Chien

John P Jordan

John P Jordon

The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.

Electronically diagnosing a component in a process line using a substrate signature

System and method for creating a substrate signature

Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N , O , and a hydrocarbon. By etching the low capacitance dielectric layer with a plasma created out of the etch chemistry, fast etch rates can be obtained while also maintaining profile control and preserving critical dimension of the resultant opening (e.g., via/trench) being etched in the low capacitance layer.

Technique for etching a low capacitance dielectric layer

Convertible hot edge ring to improve low-K dielectric etch

Method for stripping photoresist from a semiconductor wafer including a layer of organosilicate dielectric. The method introduces a flow of hydrogen-containing gas to the wafer, and uses the hydrogen-containing gas to form a plasma in proximity with at least a portion of the wafer. The plasma is used to strip at least a portion of the photoresist from the wafer. Where the stripping of the photoresist from the semiconductor wafer is performed subsequent to an etching step performed on the wafer in an etch apparatus, the present invention in turn enables the stripping of the photoresist in situ within the etch apparatus. A surprising result of the present invention is that dramatically elevated concentrations of hydrogen gas not only enable high throughput strip rates, but that the utilization of these highly concentrated hydrogen gas mixtures can be performed in safety.

Post etch photoresist strip with hydrogen for organosilicate glass low-&kgr; etch applications

Method for etching dual damascene structures in organosilicate glass

Two-step process to improve low-K dielectric etch uniformity, apparatus to perform the method, and semiconductor devices formed in accordance with the method. In a first etching step, an insulating hot edge ring is provided. When the photoresist clearing signal is observed using end-point software, the insulating cover is moved aside to expose the conductive edge ring for the remainder of the etch. One aspect of this invention contemplates an insulator cover over a conductive edge ring at the start of wafer etching, which cover is removed after end-pint detection. The present invention contemplates a number of physical configurations whereby the insulator ring is urged into, and away from, its masking of the conductive edge ring. Alternatively, the etching of a wafer bearing low-K material may be conducted using two edge rings, where the first etch step is conducted using an insulating hot edge ring, and a second etch step is conducted using a conductive hot edge ring. According to this aspect, the two step process may thus be performed in a plurality of reactor vessels, or in one reactor vessel having a plurality of processing stations. Different low-K materials may require differing etchant/passivant/diluent combinations. Accordingly, the two-step etch process is taught in conjunction with any number of different etch chemistries.

A plasma processing chamber includes a substrate holder and a gas distribution plate having an inner surface facing the substrate holder, the inner surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The inner surface is cooled by adding a heat transfer gas such as helium to process gas supplied through the gas distribution plate. The chamber can include a dielectric window between an antenna and the gas distribution plate. The control of the temperature of the inner surface facing the substrate minimizes process drift and degradation of the quality of the processed substrates during sequential processing of the substrates such as during oxide etching of semiconductor wafers.

Apparatus for reducing process drift in inductive coupled plasma etching such as oxide layer

In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

Self-aligned contacts for semiconductor device

A plasma, formed from a mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2, is used to etch a self-aligned contact, the self-aligned contact being an opening in the oxide layer, the opening being aligned with an opening in an underlying nitride layer and extending to a substrate underlying the nitride. The mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2 provides a high ratio of oxide etch rate to nitride etch rate so that the etching is completed without substantially damaging the nitride layer. For thicker oxide layers a preliminary etch step using C.sub.2 F.sub.6 and C.sub.2 HF.sub.5 may be performed prior to using the mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2.

A method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N.sub.2 and H.sub.2 into the plasma processing chamber. There is included creating a plasma out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer in the plasma processing chamber.

Techniques for etching a low capacitance dielectric layer on a substrate

Apparatus for reducing process drift in inductive coupled plasma etching

A method in a plasma processing chamber for fabricating a semiconductor device having a self-aligned contact. The method includes the step of providing a wafer having a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above a polysilicon layer, and an oxide layer disposed above the nitride layer. The method further includes the step of etching in a first etching step partially through the oxide layer of the layer stack with a first chemistry and a first set of process parameters. In this first etching step, the first chemistry comprises essentially of CHF.sub.3 and C.sub.2 HF.sub.5. The method also includes the step of etching the oxide layer in a second etching step through to the substrate with a second chemistry comprising CHF.sub.3 and C.sub.2 HF.sub.5 and a second set of process parameters. The second set of process parameters is different from the first set of process parameters and represents a set of parameters for etching the oxide layer with a higher oxide-to-nitride selectivity than the oxide-to-nitride selectivity achieved in the first etching step.

Methods and apparatus for etching self-aligned contacts

A method of fabricating a CMOS-type structure entails forming a pair of conductive portions (68 and 70) on a pair of dielectric portions (72 and 74) lying on monocrystalline silicon (60). N-type dopant-containing ions are implanted into the silicon to form a pair of doped regions (78/82) separated by p-type material under one of the dielectric portions. Boron dopant-containing ions are similarly implanted to form a pair of doped regions (84) separated by n-type material under the other dielectric portion. A sacrificial oxidation is performed by oxidizing surface material of each conductive portion and each doped region and then removing at least part of the so oxidized material (86) down to the underlying silicon. Tungsten (88 and 90) is deposited on the exposed silicon after which a patterned electrical conductor is provided over the tungsten. Use of the sacrificial oxidation substantially reduces tunnel formation during the tungsten deposition.

Growing community of inventors

Union City, CA, United States of America

Janet M Flanner