Xilinx, Inc.

Jane W Sowards

Steven P Young

Shuxian Wu

F Erich Goetting

Jennifer Wong

Venu M Kondapalli

Raymond C Pang

Stephen M Douglass

Mehul R Vashi

Scott O Frake

Nigel G Herron

Stephen M Trimberger

Peter Rabkin

Michael J Hart

Yan E Wang

David P Schultz

Peter H Alfke

Kameswara K Rao

Schuyler E Shimanek

Amitava Majumdar

Zhiyuan Wu

Jing Jing

Xin X Wu

Wilson Kaming Yee

Albert Shih-Huai Lin

Niravkumar Patel

Min-Hsing Chen

Jonathan J Ho

Kaiman Chan

Min-Fang Ho

Jung-Ching J Ho

An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

Integrated circuit chip testing interface with reduced signal wires

An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Substrate noise isolation structures for semiconductor devices

An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.

Method and apparatus for modeling transistors in an integrated circuit design

An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d). A stress layer overlying the transistor array produces stress in a channel region of the transistor.

Techniques for improving transistor-to-transistor stress uniformity

Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.

Method and apparatus for improving a circuit layout using a hierarchical layout description

Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.

Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist

Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

Programmable gate array and embedded circuitry initialization and processing

Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

Programmable gate array having interconnecting logic to support embedded fixed logic circuitry

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

Programmable logic device with partial battery backup

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

Nonvolatile/battery-backed key in PLD

The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.

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Fremont, CA, United States of America

Jane W Sowards