Advanced Micro Devices Corporation

Jane V Oglesby

Minh Van Ngo

Ramkumar Subramanian

Christopher F Lyons

Sergey D Lopatin

Angela Tai Hui

Mark S Chang

Patrick K Cheung

Ashok M Khathuria

Matthew S Buynoski

Suzette Keefe Pangrle

James J Xie

Nicholas H Tripsas

Uzodinma Okoroanyanwu

Terence C Tong

Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.

Sidewall formation for high density polymer memory element array

The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

System and method of forming a passive layer by a CMP process

The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

Silicon containing material for patterning polymeric memory element

A system and methodology are disclosed for forming a passive layer on a conductive layer. The formation can be done during fabrication of an organic memory cell, where the passive layer generally includes a conductivity facilitating compound, such as copper sulfide (Cu S). The conductivity facilitating compound is deposited onto the conductive layer via plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor. The precursor facilitates depositing the conductivity facilitating compound in the absence of toxic hydrogen sulfide (H S), and at a relatively low temperature and pressure (e.g., between about 400 to 600 K and 0.05 to 0.5 Pa., respectively). The deposition process can be monitored and controlled to facilitate, among other things, depositing the conductivity facilitating compound to a desired thickness.

MOCVD formation of Cu2S

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

Polymer memory device formed in via opening

Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.

Methods of forming passive layers in organic memory cells

A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.

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Mountain View, CA, United States of America

Jane V Oglesby