Cisco Technology, Inc.

Viasat, Inc.

Jane Smith

Douglas Paul Kirchenbauer

Paul F Struhsaker

James Heintel

Robert A Muller

Systems and methods for automated control/monitoring code development for ASICs and PLDs are provided. Control/monitor structures associated with a module may be inputted into a standard specification file. One or more default configurations for each control/monitor structure may also be inputted into the specification file. Fields of the specification file may be automatically populated or updated in response to user input in another field, and input and consistency errors may be automatically detected and/or corrected. After a request to build a module is received, one or more source or header output files may be automatically generated using information from the specification file. Automatically generated documentation may also be inserted into the output files, and links may be generated to and from hardware specifications and programmer's manuals.

Control/monitor automation for ASICs and programmable logic

A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation and subsequent parity error reporting. The specific location of where the error occurred can be stored to enable software to correct and/or reconfigure the registers. The HA hardware verifies the validity of control and configuration registers coupled to a bus, utilizing idle cycles in addition to valid bus cycles so there is no impact on system throughput.

Automated hardware parity and parity error generation technique for high availability integrated circuits

A correlation system for use in wireless direct sequence spread spectrum systems includes a RF down converter which receives an encoded RF signal and generates therefrom analog in-phase (I) and quadrature (Q) signal components. These components are digitized and the digitized signals are then passed to each of the high precision correlator circuit and a low precision correlator circuit. The low precision correlator circuit consist of a bank of a plurality of low precision correlators which receive the I and Q signal components as inputs and correlates the same with progressively phase shifted or delay pseudo noise (PN) codes. A low precision correlation circuit locks on to the appropriate PN code phase shift or delay and applies the same as a reference PN code to the high precision correlation circuit for data acquisition and demodulation.

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Akron, OH, United States of America

Jane Smith