Infineon Technologies Ag

Siemens Aktiengesellschaft

J&uuml;rgen Lindolf

Helmut Schneider

Thoai-Thai Le

Florian Schamberger

Matthias Lehr

Robert Kaiser

Jochen M&uuml;ller

Kamel Ayadi

Bernhard Sell

Hermann Ruckerbauer

Dominique Savignac

Helmut Fischer

Martin Popp

Axel Brintzinger

Joachim Schnabel

Thilo Schaffroth

Eckhard Brass

Stefan Dankowski

Ulrich Frey

Thomas Borst

Rene Tews

J&ouml;rg Peter

Stefanie Schatt

Nedim Oezoguz-Geissler

An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Integrated circuit having a programmable element and method of operating the circuit

A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

Transistor configuration for a bandgap circuit

A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

Fuse for a semiconductor configuration and method for its production

An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided into defect-free groups having exclusively defect-free memory cells and into defective groups having at least one defective memory cell. The memory further includes a memory configuration table that contains a list of the defect-free groups and an assignment unit that, based upon the entries in the memory configuration table, executes memory accesses only to those memory cells assigned to a defect-free group. The total capacity of the memory module, then, is not fixed once and for all with fabrication, but, rather, results only after a memory test, or may even vary in the course of the module lifetime.

Integrated dynamic memory and method for operating it

A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

Vertical field effect transistor with internal annular gate and method of production

A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

Circuit configuration and method for determining a time constant of a storage capacitor of a memory cell in a semiconductor memory

Electrical fuses/antifuses in a semiconductor memory configuration, such as in particular a DRAM, are read, instead of with the previously conventional internal voltage, with the voltage that defines the high potential of the bit lines of a memory cell array in the semiconductor memory. The high potential of the bit lines is defined by a voltage that is reduced relative to the internal voltage of the semiconductor memory.

Method of reading electrical fuses/antifuses

A circuit configuration for measuring the capacitance of structures in an integrated circuit having a test structure and a reference structure, includes first and second series circuits, each having two transistors connected in series and connected in parallel between supply terminals each providing one supply potential. The test structure is connected to a coupling node of the transistors of the first series circuit. The reference structure is connected to a coupling node of the transistors of the second series circuit. The supply terminals of the series circuits are connected to a controllable voltage source. A voltage-dependent differential capacitance measurement can be carried out on the test structure by using the circuit configuration.

Circuit configuration for measuring the capacitance of structures in an integrated circuit

The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate ( ); providing a metallization region ( ) comprising a first metal in the circuit substrate ( ); providing a first insulation layer ( ) above the metallization region ( ); forming an opening ( ) in the insulating layer ( ) in order to uncover at least part of the surface of the metallization region ( ); depositing a functional layer ( &prime;) above the resulting structure; depositing a second insulating layer ( ) above the resulting structure, in such a manner that the opening ( ) is filled; polishing-back of the second insulating layer ( ) and of the functional layer ( &prime;) in order to uncover the surface of the first insulating layer ( ); forming a contact ( &prime;) in the second insulating layer ( ) inside the opening ( ) in order to make contact with the functional layer ( &prime;); and providing an interconnect ( ) for electrical connection of the contact ( &prime;).

Method for fabricating an integrated circuit, in particular an antifuse

A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.

Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration

In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Semiconductor circuit configuration

A circuit configuration is described that has a first voltage terminal, a second voltage terminal and a control input. A reference-ground potential is applied to the first voltage terminal and an operating voltage is applied to the second voltage terminal. The control input is supplied with a control voltage, the control voltage assumes voltage values which alternate between the reference-ground potential and the operating voltage. The alternation of the control voltage has the effect that components such as transistors and inverter that are present in the circuit configuration are active and thereby experience an accelerated aging process in order to stabilize the threshold voltage of the MOS transistor.

Method for carrying out a burn-in process for electrically stressing a semiconductor memory

A connection element in an integrated circuit having a layer structure disposed between two conductive structures. The layer structure is formed by an insulating layer, which can be destroyed by application of a predetermined voltage, and a silicon layer. The insulating layer adjoins a first conductive structure made of tungsten.

Connection element in an integrated circuit having a layer structure disposed between two conductive structures

A sense amplifier configuration includes a semiconductor substrate, a well having a variable well potential and insulated in the semiconductor substrate, and at least one field-effect transistor in the well. The transistor has a short channel length and an adjustable threshold voltage. Locating the field-effect transistor in an insulated well with a controllable potential allows for compensation of deviations in the threshold voltage with the substrate control effect. The threshold voltage can increase with increasingly larger negative voltage values of the well potential. The threshold voltage has an actual value and a target value, and the well potential can be controlled as a function of a difference between the actual and target threshold voltage values. The well potential can vary from approximately &plus;200 mV to &minus;400 mV, and in steps of approximately 50 mV. The field-effect transistor has a switched-off state, and the well potential can be different from an active potential in the switched-off state of the field-effect transistor, preferably, the well potential is 0 V in the switched-off state. The field-effect transistor can be a plurality of field-effect transistors all disposed in the well. The semiconductor substrate, the well, and the field-effect transistor can be fabricated by ion implantation.

Growing community of inventors

Friedberg, Germany

Jürgen Lindolf

Growing community of inventors

Friedberg, Germany

J&uuml;rgen Lindolf

Jürgen Lindolf