Other

Nec Corporation

J&ouml;rg Henkel

Haris Lekatsas

Wayne A Wolf

The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.

Method and apparatus for adaptive bus coding for low power deep sub-micron designs

A code compression method and apparatus for system-level power optimization that lessens the requirements imposed on main memory size. The apparatus utilizes a post-cache architecture that has a decompression engine that decompresses compressed object code instructions using dictionary look-up tables, branching instruction controllers and mathematical derivations based on bit toggling. The decompression engine extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.

Method and apparatus for object code compression and decompression for computer systems

A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions. The invention also has an apparatus utilizing a post-cache architecture that has a decompression engine that decompresses instructions that have been compressed using the method of the invention. The apparatus extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.

Growing community of inventors

Princeton, NJ, United States of America

Jörg Henkel

Growing community of inventors

Princeton, NJ, United States of America

J&ouml;rg Henkel

Jörg Henkel