Force10 Networks, Inc.

Dell Products Inc.

Janardhanan P Narasimhan

Krishnamurthy Subramanian

Thayumanavan Sridhar

Raja Sathianarayan Jayakumar

Joyas Joseph

Purushothaman Nandakumaran

Sanjeev Agrawal

A LAN includes a CORE switch, some number of TOR switches, each linked to the CORE switch, and each of the TOR switches are linked directly to some number of host devices. Each of the switches in the LAN operate to process and transmit data frames they receive from neighboring LAN devices. Each TOR switch in the LAN builds and maintains a layer-2 forwarding table that is comprised of MAC address information learned from frames they receive from neighboring LAN devices. Selected ports/VLAN s on some or all of the TOR devices are designated to be CORE/switch facing ports (CFP) or host facing ports (HFP). Each of the CFPs are configured to only learn the MAC address in unicast frames it receives and each of the HFPs can be configured to learn the MAC address of both unicast and multicast data frames provided the destination MAC address included in the unicast frame is known.

Limiting MAC address learning on access network switches

A network switch suitable for receiving packets of information from and the packets of information to a communications network includes a plurality of physical ports, packet processing functionality and memory. The packet processing functionality operates on information stored in memory to determine the LAG, from among two or more LAGs, over which a packet received by the switch should be correctly forwarded. The switch memory stores a plurality of LAG tables, each one of which can include one or more entries comprising a physical port number and a packet parameter that are used by the packet processing functionality to determinately identify the correct LAG over which to forward a packet.

Link aggregation based on port and protocol combination

A LAN includes a CORE switch linked to some number of TOR switches, and each of the TOR switches are linked directly to some number of host devices. Each of the switches in the LAN operate to process and transmit data frames they receive from neighboring LAN devices. Each TOR switch in the LAN builds and maintains a layer-2 forwarding table that is comprised of MAC address information learned from frames they receive from neighboring LAN devices. Selected ports/VLANs on some or all of the TOR devices are designated to be CORE/switch facing ports (CFP) or host facing ports (HFP). Each of the CFPs are configured to only learn the MAC address in unicast frames it receives and each of the HFPs can be configured to learn the MAC address of both unicast and multicast data frames provided the destination MAC address included in the unicast frame is known.

Two network switches are configured in a stacked relationship to each other and include link aggregation sub-layer functionality. Switching tables are programmed on each switch with information used to forward packets ingressing to them over a redundant LAG that is identified in the switching table by a port that is a member of the redundant LAG.

Method and apparatus for configuring a link aggregation group on a stacked switch

A virtual chassis includes two or more physical chassis and operates as a single, logical device. Each of the two or more physical chassis include two route processor modules (RPM) and each RPM is assigned a first and a second role within the virtual chassis. The first role is a physical chassis level role and the second role is a virtual chassis level role. The RPMs operate in coordination such that the failure of any one of the RPMs results in one or more other RPMs taking over the first and second roles of the failed RPM.

Highly available virtual packet network device

A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Growing community of inventors

Chennai, India

Janardhanan P Narasimhan