International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Globalfoundries U.S. 2 LLC

Janak G Patel

David Brian Stone

Peter Slota, Jr

Mark C Lamorey

Luke D Lacroix

Mark C H Lamorey

David John Russell

Nazmul Habib

Richard Stephen Graf

Shidong Li

Douglas Oliver Powell

Manish Nayini

William Louis Brodsky

Subramanian Srikanteswara Iyer

David L Questad

Steven Frederick Oakland

Samuel R Connor

Kenneth Charles Marston

Daniel George Berger

Timothy W Budell

Mark Curtis Hayes Lamorey

Louis-Marie Achard

Kerry Paul Pfarr

John Edward Cronin

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Wilbur David Pricer

Jerzy Maria Zalesinski

William E Bernier

Rajneesh Kumar

Michel S Michail

Dennis A Schmidt

Marcus E Interrante

Kathryn C Rivera

Chenzhou Lian

Dana J Thygesen

Dana John Thygesen

Samantha Donovan

A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.

Heat sink configuration for multi-chip module

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

IC chip package with dummy solder structure under corner, and related method

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Shielded package assemblies with integrated capacitor

A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Reduced-warpage laminate structure

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

Thermally enhanced package to reduce thermal interaction between dies

Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.

Heat sink attachment on existing heat sinks

Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic component, a peripheral region configured to be coupled with a substrate, and a connecting region arranged between the central region and the peripheral region. The connecting region is configured to impart stress relief to the central region.

Flexible heat spreader lid

Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures

Growing community of inventors

South Burlington, VT, United States of America

Janak G Patel