Cypress Semiconductor Corporation

Koninklijke Philips Corporation N.v.

Nxp B.v.

Parade Technologies, Ltd.

Entropic Communications, Inc.

Nytell Software LLC

Jan-Willem Van De Waerdt

Hans Van Antwerpen

Viktor Kremin

Stephan Rosner

Jean-Paul Vanitegem

Roland Richter

Bart Decanne

Christian Wiencke

Carlos Basto

Andriy Maharyta

Oleksandr Karpin

Igor Kolych

Abraham Karel Riemens

Paul Kelleher

Volodymyr Bihday

Paul Stravers

Ihor Musijchuk

Milton Ribeiro

Kai Dieffenbach

Pieter Van Der Wolf

Aaron Hogan

Venkat Natarajan

Steven Roos

Uwe Moslehner

Johan Gerard Willem Maria Janssen

Jens Wagner

Mathias Sedner

Milton D A Ribeiro

Colm O'Keeffe

Paulus Stravers

Maurice Penners

A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying 'event' activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Microcontroller energy profiler

A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (CPUs), memory array or portions of arrays, and peripherals.

Context-based protection system

A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying 'event' activities, where the energy consumed by the component may be determined by the number of events executed by the component, and 'duration' activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Encryption for XIP and MMIO external memories

Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Encryption/decryption techniques for external memory are described herein. In an example embodiment, a device comprises an internal memory and an external memory controller. The internal memory is configured to store a key. The external memory controller is configured to encrypt, with the key, an address for an access operation to an external memory device to obtain an encrypted address, and to encrypt or decrypt a block of data for the access operation based on the encrypted address.

Encryption method for execute-in-place memories

Apparatus and methods of de-convolution for multi-phase scans of an array of electrodes are described. One programmable circuit includes a sequencer to initiate a multi-phase transmit (TX) scan of an array of electrodes to obtain capacitance data. The capacitance data is stored in one or more storage devices as convoluted capacitance data. The programmable circuit also includes a digital circuit block to read the convoluted capacitance data from the one or more storage devices, de-convolve the convoluted capacitance data to obtain de-convoluted capacitance data, and store the de-convoluted capacitance data in the one or more storage devices.

Hardware de-convolution block for multi-phase scanning

Capacitive touch sensors and touchscreen data processing methods are provided. In one embodiment, the method includes sequentially integrating and converting charge from each of a plurality of sensing capacitors in an array to digital data, the digital data including sample values corresponding to a measured capacitance for each of the plurality of sensing capacitors. Noise is then separated from useful information by filtering the sample values on a sample-by-sample basis. Finally, the filtered sample values are summed and a position of at least one contact on the array determined using the filtered capacitance values. Other embodiments are also provided.

Touchscreen data processing

A contact's interaction with a sensing array is subject to several external and internal stimuli which may impact a processing unit's confidence in the characteristics of that interaction or the presence of the interaction itself. Fidelity of user action is greatly improved with a step-wise and holistic analysis of a contact on an array of capacitance sensors, which allows for repetition of certain steps of processing or the entire operation if threshold confidence levels are not achieved.

Hardware accelerator for touchscreen data processing

Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel.

Interface and synchronization method between touch controller and display driver for operation with touch integrated displays

Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.

Pipelined processor and compiler/scheduler for variable number branch delay slots

A cache management policy is provided, comprising a method for writing back to a memory () a data element set () stored in a cache (). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.

Cache management policy and corresponding device

A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Translation lookaside buffer

A method of producing an integrated circuit () using a system-on-chip (SoC) architecture includes providing a first circuit () in a first island of synchronicity (IoS); and providing a source-synchronous data link () between the first circuit () in the first IoS and a hard core () in a second IoS for communicating n-bit data elements between the first circuit () and the hard core (). The source-synchronous data link () includes a set of n data lines () for transporting the n-bit data elements between the first circuit () and the hard core (), and a source-synchronous clock line () for transporting a source clock between the first circuit () and the hard core () for clocking the n-bit data elements. The hard core () does not include a bus interface adaptor for interfacing with the source-synchronous data link ().

Growing community of inventors

San Jose, CA, United States of America

Jan-Willem Van De Waerdt