Taiwan Semiconductor Manufacturing Comp. Ltd.

Jan-Wen You

Burn Jeng Lin

Jaw-Jung Shin

Chang-Ming Dai

Chung-Hsing Chang

Tsai-Sheng Gau

Burn-Jeng Lin

King-Chang Shu

Li-Jui Chen

Li-Chun Tien

Shih-Ming Chang

Chun-Kuang Chen

Wen-Chuan Wang

Mi-Chang Chang

Yu-Jun Chou

Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.

Method and system for identifying lens aberration sensitive patterns in an integrated circuit chip

An image processing system. An input/output device receives information for pixels in an image corresponding to an object, wherein the information specifies optical properties. A storage device stores the information. A processor determines an image of preliminary contour of the object based on the information. For pixels located on the preliminary contour are assigned as primary pixels, wherein anchor points determined by the location of the primary pixels, and the reference pixels determine modification vectors according to the information corresponding to the primary and reference pixels, and adjusts the positions of the anchor points according to the modification vectors. These processes are applied on every pixels or selected pixels located on the preliminary contour repeatedly to determine the final modified contour with sub-pixel accuracy.

Method and system for enhancing image resolution using a modification vector

A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

Method for improving the critical dimension uniformity of patterned features on wafers

Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.

Phase shift assignments for alternate PSM

A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is &#xbc; to &#xbd; the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era

Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution ERA

A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

Method of defining forbidden pitches for a lithography exposure tool

A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is &frac14; to &frac12; the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

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Jhongli, Taiwan

Jan-Wen You