U.S. Philips Corporation

Jan W Slotboom

Marcellinus J Pelgrom

Hendrik A Harwig

Henricus G Maas

Johannes A Appels

Pierre Hermanus Woerlee

Arie Slob

Reinout Woltjer

Geert J Davids

Francois M Klaassen

Rudolph M Snoeren

Godefridus A M Hurkx

Andreas Hubertus Montree

Adam R Brown

Marcellinus J Annegarn

Johannes G Raven

Wiebe B De Boer

Godefridus A Hurkx

Kazimierz Osinski

Albert Schmitz

Hendrik C De Graaff

Wiegert Wiertsema

Lakshmi N Sankaranarayanan

Paul A Hart

Arjen G Van Der Sijde

Kazimierz Osinki

Karel E Kuyk

A semiconductor device with a tunnel diode (,) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (,) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (,A,,A) of the semiconductor regions (,) adjoining the junction (,) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (,). The tunnelling efficiency is substantially improved as a result of this, and also because of the reduced bandgap of said portions (,A,,A), and the device according to the invention has a much steeper current-voltage characteristic both in the forward and in the reverse direction. This opens perspectives for inter alia an attractive application where the tunnelling pn junction (,) is used as a transition between two conventional diodes, for example pn or pin diodes, which are used one stacked on the other and which can be formed in a single epitaxial growing process thanks to the invention. The portions (,A,,A) adjoining the tunnelling junction (,) are preferably 5 to 30 nm thick and comprise between 10 and 50 at % germanium. The doping concentration may be 6&times;10,or even more than 10,at/cm,. The invention further relates to a simple method of manufacturing a device according to the invention. This is preferably done at a temperature of between 550&deg; C. and 800&deg; C.

Semiconductor device with a tunnel diode and method of manufacturing same

Very high resistance values may be necessary in integrated circuits, for example in the gigaohm range, for example for realizing RC times of 1 ms to 1 s. Such resistance values cannot or substantially not be realized by known methods in standard i.c. processes because of the too large space occupation. In addition, known embodiments are usually strongly dependent on the temperature. According to the invention, therefore, two zener diodes (10, 4; 11, 4) connected back-to-back are used as the resistor. The current through each zener diode is mainly determined by band--band tunneling when the voltage is not too high, for example up to approximately 0.2 V. This current has a value such that resistors in the giga range can be readily realized on a small surface area. Since the current is mainly determined by intrinsic material properties of silicon, the temperature dependence is very small. The resistor may furthermore be manufactured in any standard CMOS process or bipolar process.

Semiconductor resistor using back-to-back zener diodes

A semiconductor device includes a programmable element having a doped semiconductor region (4) and a conductor region (6) which are separated from one another by at least a portion of an insulating layer (5). The conductor region (6) is of a material suitable for forming a rectifying junction (8) with the material of the semiconductor region (4). To achieve a comparatively high conductivity connection to the semiconductor region (4), the element is further provided with a contact region (3) which has a comparatively low electrical resistance compared with the semiconductor region (4). The contact region (3) is provided at a side of the semiconductor region (4) remote from the insulating layer (5) and is separated from the insulating layer (5) by the semiconductor region (4). Both the semiconductor region (4) and the contact region (5) are laterally bounded by an isolating region (7) at opposing sides. The invention thus offers a device provided with a programmable element of a substantially more compact structure than a comparable conventional programmable element.

Semiconductor device provided having a programmable element with a

A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) connected to a first supply line (151) and has a collector region (14) connected to a second supply line (152) through a load (16). A constant potential difference is maintained between the two supply lines (151, 152) during operation. The collector region (14) is laterally electrically insulated and provides a feedback to the control transistor in such a manner that, during operation within a certain voltage domain, a change in the voltage difference between the emitter region (12) and the collector region (14) leads to an opposite change in the conductivity through the control transistor.

Semiconductor device having a programmable memory cell

A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.PROG can be applied between the column and row conductors associated with the element to be programmed during operation, which voltage is greater than the breakdown voltage of at least a portion of the insulating layer (8) situated between the semiconductor region (10) and the conductor region (20) of the element. The programming voltage is applied with such a polarity that majority charge carriers in the semiconductor region (10) are drawn to an interface (4) between the semiconductor region (10) and the insulating layer (8), forming an accumulation layer (31) there. Between the remaining column and row conductors, on the other hand, the programming voltage is offered with an opposite polarity. Thus the programming of the matrix can take place, if so desired, by means of only a single voltage level V.sub.PROG.

Semiconductor device provided with a number of programmable elements

An x-ray examination apparatus includes an imaging arrangement, devised for performing fluoroscopy. Which has image sensors that are efficiently optically coupled with an x-ray sensitive radiation conversion screen. Consequently, the image sensors produce an electrical signal having a high signal-to-noise ration when low doses of x-radiation are administered. An x-ray conversion screen is provided with a tapetum filter so as to concentrate light in the forward direction. Furthermore, the x-ray conversion screen is preferably fitted with a light reflecting layer for reflecting light that has been reflected by the tapetum filter, said light reflecting layer being transparent for x-radiation. Further concentration of light in the forward direction is achieved by placing a light-transparent material having a suitable refractive index between the radiation conversion screen and lenses that concentrate the light onto the image sensors. Semiconductor image sensors in the form of charge-coupled devices are provided for converting a visible image into an electronic video signal. In order to improve the effectiveness of the CCDs, weak avalanching is applied so as to increase both sensitivity and signal-to-noise ratio of the sensors.

X-ray examination apparatus with an imaging arrangement having a

A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode. Second, third, fourth and fifth charge transfer electrodes (25, 26, 27 and 28) are provided to transfer charge packets between sites beneath, respectively, the first storage electrode (21) and the second row (22b), the first row (21b) and the second storage electrode (22), the second storage electrode (22) and the fourth row (23b), and the third row (22c) and the third storage electrode (23). The first, second and third storage and associated transfer electrodes may form an output stage (20) of a parallel register (C) of a series-parallel-series device to enable de-interlacing of rows of information.

Charge-coupled device

A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.

Charge-coupled semiconductor device having an improved electrode

A method of detecting binary information from the pulse-shaped output signal of a CCD uses a varying reference voltage which depends on the amplitude of the last pulse detected, in order to render the detection system immune to pulse distortion as a result of transfer losses in the CCD.

Detecting binary information from a charge transfer device

A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations of the de-interlacing electrodes, and associated complex clock control, a narrow extra electrode (41) is provided between the de-interlacing electrodes and the series-output register (B). This electrode (41) may serve as a buffer electrode for each half row of information (from 1a or 1b) while the preceding half row (from 1b or 1a) is transported through the series output register.

Charge-coupled device having a buffer electrode

In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

Charge coupled devices having narrow coplanar silicon electrodes

The invention relates to a charge-coupled device, in which the reset transistor of the output is clocked--with a positive threshold voltage--by a maximum voltage equal to the supply voltage V.sub.DD. The drain (14) of the reset transistor is adjusted by means of an auxiliary transistor (T.sub.1) controlled by a current source (T.sub.2) and having the same threshold voltage, whose gate (21) is applied to V.sub.DD and whose source (22) is connected to the drain (14) of the reset transistor. Due to the fact that the maximum gate voltage is equal to V.sub.DD, additional voltage sources, such as charge pumps, for generating voltages higher than V.sub.DD are superfluous.

Charge transfer device output

The invention relates to an integrated MOS circuit comprising a MOS transistor which is connected as a resistor and which, when conducting current, generates a voltage which is supplied to the source/gate of a second field effect device. In order to obtain a suitable current adjustment, the two channel widths are chosen so that due to narrow channel effects, a difference (though small) in threshold voltage is obtained. The invention is of particular interest for CCD input circuits for generating a small offset voltage required for supplying FAT-zero.

Semiconductor device for obtaining an accurate threshold voltage

A method of manufacturing a semiconductor device having narrow, coplanar, silicon electrodes which are separated from each other by grooves or slots having a width in the submicron range. The electrodes are alternatively covered by an oxide and by an oxidation-preventing layer, such as silicon nitride. According to the invention, a first and second electrode which are both covered with one of these layers, and which enclose a third electrode covered by the other of these layers, are first interconnected inside a connection region. Two of the three electrodes are separated from the connection region by etching. By selective etching, overlapping contact windows are provided on all three electrodes, and inside the contact windows etching of the groove is omitted.

Method of manufacturing a semiconductor device and device manufactured

In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

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Eindhoven, Netherlands

Jan W Slotboom