Abb Technology Ag

Abb Schweiz Ag

Hitachi Energy Ltd

Abb Power Grids Switzerland Ag

Audi Ag

Jan Vobecky

Munaf Rahimo

Arnost Kopta

Umamaheswara Vemulapati

Marco Bellini

Martin Arnold

Wolfgang Janisch

Jagoda Dobrzynska

Florin Udrea

Lise Donzel

Iulian Nistor

Jürgen Schuderer

Tobias Wikstroem

Juergen Schuderer

David Guillon

Hamit Duran

Paul Commin

Virgiliu Botan

Karlheinz Stiegler

Neophythos Lophitis

Lulian Nistor

Marta Cammarata

Frank Ritchie

Kati Hemmann

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

Power semiconductor device

A power semiconductor device includes a semiconductor wafer having a junction and a junction termination laterally surrounding the junction. A protection layer covers the lateral side of the semiconductor wafer and covers the second main side at least in an area of the junction termination. A first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer. An interface between the first metal disk and the semiconductor wafer is a free floating interface. A metal layer sandwiched between the first metal disk and the semiconductor wafer.

Power semiconductor device with free-floating packaging concept

A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Power semiconductor module

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Bidirectional phase controlled thyristor (BiPCT)&#x2014;a new semiconductor device concept

The present application relates to a power semiconductor device, including a substrate having a first side and a second side, the first side and the second side being located opposite to each other, wherein the first side includes a cathode and the second side includes an anode, wherein a junction termination of a p/n-junction is provided at at least one surface of the substrate, preferably at at least one of the first side and the second side, the junction termination is coated by a passivating coating, the passivating coating including at least one material selected from the group consisting of an inorganic-organic composite material, parylene, and a phenol resin comprising polymeric particles. A device as described above thus addresses issues of passivation of junction terminations and thus prevents or at least reduces the danger of fatal defects such as unstable device operation caused by changes in film properties, instability, water permeability, permeability of movable ions such as sodium, pinholes and cracks, and aluminum metal disconnection or corrosion due to degradation and stress.

Power semiconductor device and method for producing a power semiconductor device

A thyristor is disclosed with a plurality of emitter shorts at points in the cathode region. The points define a Delaunay triangulation with a plurality of triangles. For a first subset of triangles a coefficient of variation of the values qwith l&#x2208;Sis smaller than 0.1, and/or an absolute value of a skewedness of the geometric quantities qwith l&#x2208;Sis smaller than 5, and/or a Kurtosis of the geometric quantities qwith l&#x2208;Sis smaller than 20. For a second subset of triangles, a quotient of a standard deviation of the quantities qwith m&#x2208;Sand a mean squared value of the geometric quantity qwith l&#x2208;Sis less than 1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0&#xd7;10.

Phase control thyristor

There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gate structure.

Thyristor with improved plasma spreading

A method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided. The following manufacturing steps are performed: a) providing an n-doped silicon carbide substrate, b) epitaxially growing a silicon carbide n-doped drift layer on the substrate, which has a lower doping concentration than the substrate, c) creating at least one p-doped termination layer by implanting a second ion up to a maximum termination layer depth and annealing on the first main side, d) forming a doping reduction layer having a depth range, which doping reduction layer comprises at least one doping reduction region, wherein a depth of a doping concentration minimum of the doping reduction layer is greater than the maximum termination layer depth, wherein for the creation of each doping reduction region: implanting a first ion with an implantation energy in the drift layer at least in the edge region, wherein the first ion and the at least one implantation energy are chosen such that the doping reduction layer depth range is less than 10 &#x3bc;m, e) annealing the doping reduction layer, wherein step d) and e) are performed such that the doping concentration of the drift layer is reduced in the doping reduction layer.

Method for manufacturing an edge termination for a silicon carbide power semiconductor device

The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode. The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region. The thickness of the first layer increases linearly over the transition region with a width of the transition region greater than 5 times a thickness of the first section of the first layer.

Bipolar non-punch-through power semiconductor device

A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w'), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w&#x2032;) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.

Reverse conducting power semiconductor device

A reverse-conducting power semiconductor device with a wafer has first and second main sides which are arranged opposite and parallel to each other. The device includes a plurality of diode cells and a plurality of gate commutated thyristors (GCT) cells. Each GCT cell includes layers of a first conductivity type (e.g., n-type) and a second conductivity type (e.g., p-type) between the first and second main sides. The device includes at least one mixed part in which diode anode layers of the diode cells alternate with first cathode layers of the GCT cells. In each diode cell, a diode buffer layer of the first conductivity type is arranged between the diode anode layer and a drift layer such that the diode buffer layer covers lateral sides of the diode anode layer from the first main side to a depth of approximately 90% of the thickness of the diode anode layer.

Reverse-conducting power semiconductor device

A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Fast recovery diode

A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration N, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: wherein a punch-through voltage Vof the semiconductor device is between 70% and 99% of a break down voltage Vof the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Punch-through semiconductor device and method for producing same

An exemplary bipolar non-punch-through power semiconductor device includes a semiconductor wafer and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer has an inner region with a wafer thickness and a termination region that surrounds the inner region, such that the wafer thickness is reduced at least on the first main side with a negative bevel. The semiconductor wafer has at least a two-layer structure with layers of different conductivity types, which can include a drift layer of a first conductivity type, a first layer of a second conductivity type at a first layer depth and directly connected to the drift layer on the first main side and contacting the first electrical contact, and a second layer of the second conductivity type arranged in the termination region on the first main side up to a second layer depth.

A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000&#xb0; C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600&#xb0; C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface.

Growing community of inventors

Lenzburg, Switzerland

Jan Vobecky