Imec

Jan Van Olmen

Serge Vanhaelemeersch

Cedric Huyghebaert

Marleen Van Hove

Herbert Struyf

Werner Boullart

Jan Vaes

Dirk Hendrickx

The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (), comprising active components on the surface of said substrate, depositing a top layer () of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening () at least through said top layer, filling said opening(s) at least with a first conductive material (), and performing a first CMP step, to form said first conductive structures (), etching at least one second opening () at least through said top layer, filling said opening(s) at least with a second conductive material (), and performing a second CMP step, to form said second conductive structures (), wherein the method comprises the step of depositing a common CMP stopping layer () on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The disclosure is equally related to devices obtainable by the method of the disclosure.

Method for producing interconnect structures for integrated circuits

A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Dual damascene patterning method

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Boutersem, Belgium

Jan Van Olmen