Texas Instruments Corporation

Jan-Tore Marienborg

Ruchi Shankar

Robin Osa Hoel

Per Torstein Røine

Stefan Dannenberger

Oddgeir Fikstvedt

Patrick Seem

Tobias Edström

Gregory Arndt

Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.

Split rail power supply architecture

A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based &#x394;&#x3a3; ADC) includes a VCO-based quantizer that includes delay elements to provide VCO outputs based on an analog input signal and combining logic to combine the VCO outputs so as to provide quantized outputs. Detection logic detects saturation of the VCO-based quantizer based on the quantized outputs and at least a portion of the VCO outputs. The VCO-based &#x394;&#x3a3; ADC also includes correction logic to modify the quantized outputs and provide modified quantized outputs in response to the detection logic detecting the saturation of the VCO-based quantizer and to provide the quantized outputs unmodified in the absence of saturation being detected.

Overload detection and correction in delta-sigma analog-to-digital conversion

A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Analog-to-digital converter

Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a plurality of multiplexers connected in series with the clock signal, each having a plurality of inputs of different phase delays. The apparatus also includes a delta sigma modulator connected to control inputs on the plurality of multiplexers. The delta sigma modulator is adapted to repeatedly select different ones of the pluralities of inputs of different phase delays in the plurality of multiplexers to change a divide ratio between the clock signal and an output of the plurality of multiplexers. The apparatus also includes a multiplexer usage accumulator connected to the delta sigma modulator to track usage of the plurality of multiplexers. The apparatus also includes a scrambler circuit connected between the delta sigma modulator and the control inputs on the plurality of multiplexers, adapted to control settings in the plurality of multiplexers based at least in part on the multiplexer usage accumulator.

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Oslo, Norway

Jan-Tore Marienborg