Nxp B.v.

Nexperia B.v.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Koninklijke Philips Corporation N.v.

Jan Sonsky

Johannes Josephus Theodorus Marinus Donkers

Jeroen Antoon Croon

Godefridus Adrianus Maria Hurkx

Anco Heringa

Philip Rutter

Matthias Rose

Evelyne Gridelet

Stephan Heil

Roel Daamen

Peter G Steeneken

Erwin Hijzen

Philippe Meunier-Beillard

Wibo Daniel Van Noort

Andreas Bernardus Maria Jansman

Coenraad Cornelis Tak

Tim Boettcher

Markus Mueller

Stephen John Sque

Stephan Bastiaan Simon Heil

Gerard Koops

Gerben Doornbos

Steven Thomas Peake

Radu Surdeanu

Prabhat Agarwal

Henricus Cornelis Johannes Buthker

Viet Thanh Dinh

Pierre Goarin

Michael A A In 't Zandt

Jan Claes

Yan Lai

Barry Wynne

Saurabh Pandey

Mark Andrzej Gajda

Almudena Huerta

Lasse Juhana Kauppinen

Godefridus Andrianus Maria Hurkx

A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.

Gallium nitride/ aluminum gallium nitride semiconductor device and method of making a gallium nitride/ aluminum gallium nitride semiconductor device

A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, and a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas forms adjacent to the interface. The device also includes a first terminal electrically coupled to a first area of the interface between the first layer and second layer and a second terminal electrically coupled to a second area of the interface between the first layer and second layer. The device also includes an electrically conducting channel comprising an implanted region at bottom and sidewalls. The electrically conducting channel is filled with a metal and the electrically conducting channel connects the second terminal and a region of the first layer such that electric charge can flow between the second terminal and the first layer.

Low resistance and leakage device

A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.

Semiconductor device and method of making a semiconductor device with passivation layers providing tuned resistance

A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.

Semiconductor device having a dielectric layer with different thicknesses and method for forming

A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.

Semiconductor device and associated methods

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

Circuitry with voltage limiting and capactive enhancement

A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.

Semiconductor device and method of making a semiconductor device

A semiconductor device comprising at least one active layer on a substrate and a first contact to the at least one active layer, the first contact comprising a metal in contact with the at least one active layer and a capping layer on the metal, the capping layer comprising a diffusion barrier, wherein the capping layer is patterned to form a pattern comprising regions of the contact covered by the capping layer and regions of the contact that are uncovered.

Semiconductor device and manufacturing method

A sensor device () for detecting particles, the sensor device () comprising a substrate (), a first doped region () formed in the substrate () by a first dopant of a first type of conductivity, a second doped region () formed in the substrate () by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region () at a junction between the first doped region () and the second doped region (), a sensor active region () adapted to influence a property of the depletion region () in the presence of the particles, and a detection unit () adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region () and the second doped region (), the electric measurement being indicative of the presence of the particles in the sensor active region ().

PN junction chemical sensor

A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structuresto leave othersmasked, and then selectively etching a buried layer to form a cavityunder an active device region. The active device regionis supported by support regions in the exposed trenches. The buried layer may be a SiGe layer on a Si substrate.

Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method

Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.

Diode circuit and power factor correction boost converter using the same

A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.

Cascoded semiconductor devices

In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Semiconductor heterojunction device

Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Growing community of inventors

Leuven, Belgium

Jan Sonsky