Dialog Semiconductor B.v.

Jan Prummel

Shobak R Kythakyapuzha

Nikolaos Moschopoulos

Michail Papamichail

Mahbub Reja

Soren Rievers

A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.

Divider circuit

A device for true random number generation is disclosed. The device comprises an antenna and an analog processing unit for analog processing of a signal received from the antenna. An analog to digital (AD) converter is used for converting an analog signal generated by the analog processing unit into a digital signal. An isolation means is applied for temporarily isolating the antenna from the analog processing unit and the AD converter to generate a noise signal. A sampling means is used for sampling output values generated by the AD converter when the antenna is isolated from the analog processing unit and the AD converter. A digital processing unit is used for processing the sampled output values generated by the AD converter. The digital processing unit is configured to generate a random number based on one or more of the output values generated by the AD converter.

True random number generation in systems on chip

A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is selected with a desired settling time. A transfer function is generated based on the PLL transfer function that predicts the spurious components. A maximum level of the spurious components produced in the PLL is determined based on the maximum frequency step. If the maximum level of the spurious frequency components produced is too large, the order variable is incremented and the PLL transfer function is determined until the transfer function produces the spurious frequency components that meet the requirements. The components for a loop filter are selected based on the selected PLL transfer function. The adjustable frequency source tuning gain, the phase detector gain, the loop filter gain, and the divide factor are chosen to meet the requirements of the PLL transfer function.

Fast settling phase locked loop (PLL) with optimum spur reduction

An amplifying circuit comprises an analog amplifying circuit having an analog input for receiving an analog input signal to be amplified and an analog output for outputting an amplified analog signal, wherein the amplifying circuit comprises an implementation of a complex transfer function. A feedback circuit has a feedback circuit input and a feedback circuit output, wherein the feedback circuit comprises an implementation of an inverse transfer function that is an estimation of an inverse of at least a DC component of the complex transfer function of the analog amplifying circuit. The feedback circuit input is arranged for receiving a signal that is based on the amplified analog signal of the analog amplifying circuit. The analog circuit is arranged for receiving a bias signal that is based on the feedback circuit output.

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Eindhoven, Netherlands

Jan Prummel