Nxp B.v.

Nxp Usa, Inc.

Jan-Peter Schat

Abdellatif Zanati

Xiankun Jin

Tao Chen

Ulrich Moehlmann

Andreas Lentz

Fabrice Poulard

Henrik Asendorf

Antonius Johannes Matheus De Graauw

Michael Doescher

Maristella Spella

Giorgio Carluccio

Ling Wang

Xavier Hours

Andres Barrilado Gonzalez

Waqas Hassan Syed

Mohamed Azimane

Michael Zimin

Michael Johannes Döscher

Lei Ma

Nicolas Lamielle

Tim Lauber

The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (); and a monitoring module (). The monitoring module () is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).

Feedback system monitoring

An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.

Apparatus to cryptographically provide a digital output signal as a response to a challenge

A communication device and method are provided for communicating data, such as a cryptographic key, wirelessly to another communication device. The communication device and the other device each include an oscillator circuit portion, an inverter, a non-inverting buffer, and a switch for switching between the inverter and non-inverting buffer. A circular loop is formed wirelessly between the oscillator circuit portions of both devices by placing both communication devices near each other. A control circuit in each device measures a parameter such as frequency or waveform pattern of the circulating signal to determine how to position the switches. The oscillator circuit portions may be portions of the same oscillator distributed between the devices, such as a delay line-controlled oscillator or a chaotic oscillator. Inverting and not inverting the circulated signal changes the parameter of the signal so that it is difficult for an eavesdropper to learn the communication.

Secure key generation using a chaotic oscillator

A communications system () comprising: an antenna () that comprises a plurality of serially connected sub-antenna elements (); and a signal generator () configured to provide a transmission signal to the antenna () for propagating along the sub-antenna elements (). The transmission signal comprises a plurality of serial symbol packets. The signal generator () is configured to set the phase of the serial symbol packets such that when they align with predefined ones of the sub-antenna elements () the antenna () provides a beamformed signal.

Communications system

A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier&#x2014;random number pair is authenticated.

Integrated circuit device die with wafer/package detection circuit

A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

Securing cryptographic operations from side channel attacks using a chaotic oscillator

A method for managing operation of a circuit includes activating a trigger engine, receiving signals from a target circuit, and detecting a hardware trojan based on the signals. The trigger engine may generate a stimulus to activate the hardware trojan, and the target circuit may generate the received signals when the stimulus is generated. The trigger engine may be a scan chain which performs a circular scan by shifting bit values through a series of flip-flops including a feedback path. The target circuit may be various types of circuits, including but not limited to a high-speed input/output interface. The hardware trojan may be detected based on bit-error rate information corresponding to the signals output from the target circuit.

System and method for triggering and detecting hardware trojans

A wireless communication device is described that comprises: a receiver configured to receive wireless local area signals located within a closed area; and a processor configured to: process the received wireless local area signals; calculate a standard deviation, STD, of Amplitude Channel State Information, A CSI, of the received wireless local area signals and, in response thereto, generate at least one transmit wireless local area signal based on the calculated A CSI STD values. A transmitter is coupled to the processor and configured to transmit the at least one transmit wireless local area signal within the closed area to disrupt an attacker located adjacent the closed area from determining a location or movement of at least one of: a moving person, the at least one further wireless communication device within the closed area.

Wireless communication device and method for spying counter measures

A test apparatus and method for testing a semiconductor device. The semiconductor device includes an integrated circuit and a plurality of external radiating elements located at a surface of the device. The external radiating elements include at least one transmit element and receive element. The test apparatus includes a plunger. The plunger includes a dielectric portion having a surface for placing against the surface of the device. The plunger also includes at least one waveguide. Each waveguide extends through the plunger for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the device. The dielectric portion is configured to provide a matched interface for the electromagnetic coupling of the waveguide openings to the plurality of external radiating elements of the device.

Test apparatus and method for testing a semiconductor device

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

Apparatuses involving calibration of input offset voltage and signal delay of circuits and methods thereof

Embodiments of a method, an IC device, and a circuit board are disclosed. In an embodiment, the method involves at an IC device of the system, monitoring activity on a bus interface of the IC device, wherein the bus interface is connected to a bus on the system that communicatively couples the IC device to at least one other IC device on the system, applying machine learning to data corresponding to the monitored activity to generate an activity profile, monitoring subsequent activity on the bus interface of the IC device, comparing data corresponding to the to subsequently monitored activity to the machine learning generated activity profile to determine if a system-level Trojan is detected, and generating a notification when it is determined from the comparison that a system-level Trojan has been detected.

Methods for detecting system-level trojans and an integrated circuit device with system-level trojan detection

Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.

Combined ECC and transparent memory test for memory fault detection

The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (), the method comprising the sequential steps of: i) receiving () a request from a processor executing an application for a read or write operation at a location of the memory module () identified by an address; ii) outputting data () from, or writing to, the location of the memory module (); iii) generating () by an error detection module () a further read request for the location of the memory module () identified by the address; iv) receiving () at the error detection module () an error correction code from the memory module () for the location identified by the address; and vi) providing () by the error detection module () an alert output for the address if the error correction code indicates an error.

Memory testing

The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL () comprising: a phase comparison module (); a loop filter (); a voltage controller oscillator, VCO (); a feedback divider (); and a jitter evaluation module (), the phase comparison module () comprising a phase comparator () and a measurement module () configured to detect a metastable output in the phase comparator () over active clock cycles of application and feedback clock signals () input to the phase comparison module () and provide an output signal () to the jitter evaluation module () indicating a metastability resolution time for the phase comparator (), the jitter evaluation module () being configured to provide an output indicative of jitter based on the metastability resolution time.

PLL jitter detection

According to certain examples, a circuit-based wireless communications system provides secure access to a vehicle by way of certain circuitry configure to compare a first RF background observed for a vehicle-located RF receiver that is part of a vehicle-located circuit secured to a vehicle, with a second RF background observed for a wireless-communications vehicle-access circuit that includes another RF receiver. In response, a distance metric is generated to indicate a degree of similarity between the first RF background and the second RF background, and based on whether this metric satisfies a threshold, access to the vehicle may be granted via the wireless-communications vehicle-access circuit.

Growing community of inventors

Hamburg, Germany

Jan-Peter Schat