Teradyne, Inc.

Jan Paul Anthonie Van Der Wagt

Ronald A Sartschev

Greg Warwar

Lawrence Choi

Corbin L Champion

Grady Borders

Howard Lin

Jeffrey Wade Sanders

Allan Parks

Gregory A Kannall

Denis Zelenin

Thomas Aquinas Repucci

Nathan Nary

Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.

Apparatus and method for operating source synchronous devices

Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.

Parallel path delay line

Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.

Voltage driver circuit

Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.

Voltage driver with supply current stabilization

Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice is controlled to switchably connect a driver output to either a high voltage level or a low voltage level via a resistor, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. A calibration procedure is disclosed herein to generate a lookup table for how to selectively connect circuit slices to supply voltages given a target output voltage.

Voltage driver circuit calibration

An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.

Edge generator-based phase locked loop reference clock generator for automated test system

A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

Automated test system with edge steering

Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.

Growing community of inventors

Carlsbad, CA, United States of America

Jan Paul Anthonie Van Der Wagt