Nynex Corporation

Nynex Science & Technology, Inc.

Jan P Vancraeynest

An improved digital parallel correlator is disclosed. Illustratively, the inventive correlator utilizes a shift register which receives a signal comprising data bits encoded as chips. At each cycle of the signal, the chips in the shift register are compared to a reference sequence and the number of matches is obtained. Whenever the number of matches exceeds a fixed high threshold or falls below a fixed low threshold, indicating the presence of a binary 1 or binary 0 data bit, the chips in the shift register are set to a predetermined sequence such as the reference sequence or its complement. This amounts to correcting any chips of a bit that are received in error as soon as it is determined that the bit is a binary 1 or binary 0. This enables the high and low thresholds to be located as far as possible from the peak correlation values thereby increasing the number of chips that can be received in error.

Digital parallel correlator

A gaming apparatus for use with a telephone network which supports standard DTMF tones and to which is connected telephone stations capable of generating standard DTMF tones wherein the gaming apparatus generates and transmits DTMF tones to a calling telephone station, receives response DTMF tones from a player at the calling station and compares the transmitted and received DTMF tones to determine if there is a match.

Interactive telephone gaming system

A circuit and method is disclosed for recovering the transmitter clock at a receiver in a direct sequence spread spectrum communication system where a transmitter and receiver run independent clocks of nominally the same frequency. At the receiver, to select the phase of the local clock that yields the strongest signal, a clock recovery circuitry cycles through M phases of the locally generated receiver clock. The cycling is halted and the phase is locked soon as an indication is obtained that a phase is valid. Alternatively, all M phases of the local clock are tested for validity or invalidity, and depending on the resulting pattern of valid and invalid phases, a particular phase is selected for the local clock. A phase is valid or invalid depending on whether there is a second correlation crossing at the expected instant one data bit period after a first correlation crossing.

Clock acquisition in a spread spectrum system

A method and apparatus for transmitting a stream of data bits in a spread spectrum format is disclosed. The inventive method comprises providing 2.sup.N predetermined spreading sequences, where N is equal to or larger than 2. The predetermined spreading sequences have suitable autocorrelation and cross-correlation properties. For each group of N bits in a stream of data bits to be transmitted, a particular one from the 2.sup.N predetermined spreading sequences is selected and transmitted. In this manner, each transmitted spreading sequence corresponds to a particular arrangement of N bits. The invention achieves an N-fold increase in data rate for a particular symbol rate by encoding N bits in a spreading sequence.

Method and apparatus for increasing the data rate for a given symbol

A combined switch and filter comprising coupled first and second quarter-wave transmission line sections and switching elements for providing selective coupling and filtering between ports of the switch coupled to the ends of the quarter-wave sections.

Combined multi-port transmit/receive switch and filter

Apparatus for generating an MSK signal by using a dual modulus frequency divider which divides an incoming digital clock signal of frequency f.sub.0 by the factors n and (n+1) in dependence on the data type of the data to be transmitted and in which the frequency f.sub.0, the data rate f.sub.d and the factor n are such as to satisfy the relationship f.sub.d =f.sub.0 .multidot.2/(n(n+1)).

Growing community of inventors

White Plains, NY, United States of America

Jan P Vancraeynest