International Business Machines Corporation

Jan Obrzut

Robert Maynard Japp

Jeffrey McKeveny

Kenneth Lynn Potter

Pamela Lulkoski

Eric A Johnson

Kostas I Papathomas

Mark David Poliks

Bernd Karl Appelt

Li Li

William Thomas Fotorny

Lawrence Robert Blumberg

Amarjit S Rai

Ross Downey Havens

Miquel A Jimarez

Keh-Chee Jen

The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.

UV absorbing glass cloth and use thereof

A fabric material and method of its manufacture suitable for use in electronic packages including chip carriers. High insulation resistance is exhibited when subjected to high temperatures and humidity stress conditions.

Laminate and method of manufacture thereof

Flip-chip electronic packages are provided with a compliant surface layer, normally positioned between an underfill layer and a substrate such as a chip carrier or a printed circuit board or card, which reduces stress and strain resulting from differences in coefficients of thermal expansion between the chip and substrate. The compliant layer, which should have a storage modulus of less than &frac12; the modulus of the substrate, preferably between about 50,000 psi and about 20,000 psi, may comprise rubbery materials such as silicone, virco-plastic polymers such as polytetrafluoroethylene or interpenetrating polymer networks (IPNs). Photosensitive IPNs used for solder marks are preferred.

Compliant surface layer for flip-chip electronic packages and method for forming same

A process determines a linear interconnection resistance R between two external access points of an electronic device. The device comprises a chip, a chip carrier and wiring between the chip and carrier. The chip comprises an ESD device such as a diode which is electrically connected between the two access points. To begin the process, various currents are injected from one of the access points to another and corresponding voltages are measured across the two access points. Alternately, various voltages are applied from one access point to the other and corresponding currents are measured. The applied voltages and injected currents all forward bias the ESD device. These current-voltage relationships are applied to an interconnection model algorithm to yield the interconnection resistance. The interconnection model algorithm is derived from an interconnection model equation using least squares as a maximum likelihood estimator applied to the interconnection model equation to deliver absolute roots of the interconnection model algorithm. The interconnection model equation models the circuit comprising the interconnection resistance and the ESD device except that the nonlinear parameters of the ESD device is untangled from the linear interconnection resistance.

Method for determining interconnection resistance of wire leads in

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Vestal, NY, United States of America

Jan Obrzut