Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Koninklijke Philips Corporation N.v.

Qualcomm Incorporated

Jan Mulder

Jan Roelof Westra

Franciscus Maria Leonardus Van Der Goes

Christopher Michael Ward

Frank Van Der Goes

Marcel Lugthart

Sijia Wang

Mohammadreza Mehrpoo

Rudy J Van De Plassche

Yee Ling Cheung

Klaas Bult

Kevin Tunghai Chan

Chi-Hung Lin

Jeffrey Allan Riley

Franciscus M L Van Der Goes

David Garrett

Rudy Van Der Plassche

Jun Cao

Dominicus Martinus Wilhelmus Leenaerts

Ali Nazemi

Adesh Garg

Hugo Veenstra

Ovidiu Bajdechi

Anand Jitendra Vasani

Giuseppe Grillo

Edwin Van Der Heijden

Burak Catli

Jiawen Zhang

Alireza Nilchi

Qiongna Zhang

Ruby Van De Plassche

Davide Vecchi

Rudy Vander Plassche

A digital-to-analog converter (DAC) calibration system comprising: a DAC configured to convert digital input to an analog input, a detector configured to measure the analog outputs of the plurality of DAC unit cells and combine the analog outputs to create an overall analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.

Circuit and method for calibration of a digital-to-analog converter

Described herein are related to a device for communication. In one aspect, the device includes a first circuit configured to generate a first signal and a second signal at a first frequency, according to a third signal at a second frequency higher than the first frequency. The first signal and the second signal may have opposite phases with each other. In one aspect, the device includes a second circuit configured to provide a difference between the first signal and the second signal as a fourth signal. In one aspect, the device includes a third circuit configured to provide the first signal to the second circuit, and resonate at a third frequency between the first frequency and the second frequency. In one aspect, the device includes a fourth circuit configured to provide the second signal to the second circuit, and resonate at the third frequency.

Intermodulation distortion suppresion circuit and method

Described herein are related to a device for communication. In one aspect, the device a first circuit configured to generate a signal. In one aspect, the device includes a port. In one aspect, the device includes a set of switches. Each switch of the set of switches may be coupled in parallel between the first circuit and the port. In one aspect, the device includes a second circuit configured to enable a subset of the set of switches, according to an amplitude of the signal.

Configurable attenuator circuit and method

Described herein are related to a device including a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal. In one aspect, the device includes a first circuit configured to generate a first signal. In one aspect, the device includes a second circuit coupled to the first circuit. The second circuit may be configured to generate a second signal, based on the first signal. The second signal may have a first edge according to the first signal. In one aspect, the device includes a third circuit coupled to the second circuit. The third circuit may be configured to generate a third signal having a second edge, in response to the first edge of the second signal. In one aspect, an amplitude of the third signal may correspond to one bit.

Circuit and method for calibration of digital-to-analog converter

Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.

Systems and method of compensating for nonlinear capacitance in converters

Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

Systems and methods of signed conversion

Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.

Calibration detector with two offset compensation loops

A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.

Fast overvoltage protection circuit with digital control

An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.

Transmitter drive with improved transmitter performance and reliability

A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Wireless transmitter using a widebrand digital-to-analog converter for processing multiple channels in a digital radio-frequency signal

A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Multi-segmented all logic DAC

Wireless transmitter using a wideband digital-to-analog converter for processing multiple channels in a digital radio-frequency signal

A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.

Overvoltage protection circuit with digital control

A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.

Efficient decoder for current-steering digital-to-analog converter

A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.

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Houten, Netherlands

Jan Mulder