U.S. Philips Corporation

Jan Lohstroh

Cornelis Maria Hart

Roelof H Salters

Joannes J Koomen

Wilhelmus J Josquin

Adrianus T Van Zanten

Cornelis M Hart

Johannes D Van Den Crommenacker

Two (polycrystalline) silicon tracks located at a relative distance of the order of submicrons which contact the subjacent semiconductor body with a pn junction formed therein, are connected to each other via a metal silicide track. The resulting shortcircuiting of the pn junction does not influence the operation of the circuit, for example, a memory cell, realized in the semiconductor body. By providing the whole conductor pattern with an oxide layer in which a contact hole is formed at the area of the shortcircuit, the latter can then be provided in a self-aligning manner.

Semiconductor device having silicon conductor tracks connected by a

A compact integrated logic circuit having an inverter transistor and several coupling diodes adjoining the collector region of said transistor. Current is applied to the base of the transistor which forms the signal input. The inverter transistor has additional means by which an effective complementary auxiliary transistor is incorporated which dissipates a considerable part of the base current in the case the inverter transistor is overdriven so that the charge storage in the inverter transistor is restricted and controlled and by which a Schottky clamp diode across the base-collector junction of the inverter transistor can be avoided.

Integrated circuit

A logic circuit of the I.sup.2 L, the ISL or the STL type having a signal input formed by the control electrode of an inverter transistor and plural signal outputs each coupled through a diode to a main electrode of the inverter transistor, this main electrode being connected to a supply line through a pull-up connection. The improvement relates to a further connection path comprising a Schottky diode and a resistor which bridges the main current path of the inverter transistor and which reduces the voltage swing at the main electrode.

Integrated logic circuit having collector node with pull-up and clamp

In a diode matrix of a permanent memory (ROM) the word line and bit line system is formed by a system of strip-shaped zones of one conductivity type provided in the silicon body and in the another system is formed by polycrystalline silicon tracks of the opposite conductivity type provided on the surface and forming mono-poly p-n junctions with the strip-shaped zones. High packing density and high speed are obtained.

ROM With poly-Si to mono-Si diodes

A memory cell for a static memory, in which the number of control lines is reduced to a maximum of three by the use of a diode in one collector circuit and the series connection of a diode and a resistor in the other collector circuit of an Eccles-Jordan flip-flop, which diodes have an exponential characteristic with an exponent smaller than that of conventional diodes.

Memory cell arrangement for a static memory

A static cross-coupled bipolar memory cell has a large read current/stand-by current ratio and short write time. The nonlinear load element includes a resistor with a parallel-connected pnp transistor serving as a diode and an inversely-operating npn transistor for dissipating charge carriers.

Static memory cell and memory constructed from such cells

A memory cell for integration into a static memory includes two transistors with cross-coupled base and collector regions. The collector regions are connected to p-n junction diode load elements having at least one region of polycrystalline silicon material. The collector regions of the transistors are connected to the regions of the diodes which are of the same conductivity type as the collector regions.

Memory cell for a static memory and static memory comprising such a cell

A read-only memory in which each memory cell is formed by two back-to-back diodes across which a connection can be formed by means of punch-through. Since cross-talk between adjacent cells is impossible, the packing density may be very large. Additionally, the cycle time of the memory is low due to the very short reverse recovery time of the invented structure.

Semiconductor device having a compact read-only memory

A photosensitive element and a photosensitive device arrangement using the element include a charge transfer structure having an electrode layer extending over a photosensitive area of a semiconductor body. In operation, a bias potential is applied to the electrode layer to form a depletion layer in the underlying body portion, and a drift field is produced in the depletion layer which extends in the direction of an edge portion of the electrode layer to permit photogenerated charge carriers to be transmitted towards the edge portion. A preferred structure for producing the desired drift field includes a resistive electrode having first and second connections for applying a potential difference along the resistive electrode. The photosensitive device arrangement further includes a localized charge-storage zone adjacent the edge portion of the electrode layer for collecting the photogenerated charge carriers and a detector circuit for measuring the charge state of the charge-storage zone.

Photosensitive device arrangement using a drift field charge transfer

A method of manufacturing a semiconductor device, in particular a monolithic integrated circuit having very small complementary transistors. According to the invention two surface zones are provided beside each other without a masking tolerance of which one is formed by diffusion from a thin silicon layer. The distance between the surface zones is determined by the width of an oxide strip formed on the surface and on the edge of the silicon layer. The oxide strip is obtained by an underetching process and by using a silicon nitride mask deposited with shadow effect.

Method of manufacturing a semiconductor device and device manufactured

A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.

Junction field effect transistor random access memory

JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.

Random access junction field-effect floating gate transistor memory

A device for reading out the charge condition of a phototransistor by means of sampling pulses, for example read out of a transistor to be selected from a matrix of phototransistors, a voltage which is a measure of said charge condition being taken from the emitter of the phototransistor. In order to avoid the storage effect owing to the time constant which depends on the differential resistance of the base-emitter-junction, the emitter circuit of the phototransistor includes a current source which at the instant of sampling is switched on, while furthermore the emitter voltage of the phototransistor is applied to a voltage comparator circuit which supplies a voltage for switching off the current source at the instant that said emitter voltage drops below a specified reference value. In the case of read-out after a dark period some charge is drained owing to the response time of electronic systems, which charge can be compensated for by simple injection means.

Device for reading out the charge condition of a phototransistor

A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.

Semiconductor floating gate storage device with lateral electrode system

A solid-state picture pick-up device according to the invention comprises a number of field effect transistors in which the channel region is bounded by two oppositely located gate electrodes each forming a rectifying junction with the channel region and in which the photosensitive junction is formed by a gate electrode which shows a floating potential. Said gate electrode may be charged by simultaneously applying to the other gate electrode a voltage pulse of a sufficiently large amplitude so that punch-through occurs between the gate electrodes. Since in this manner each transistor may be adjusted at its own threshold voltage, the influence of the spreading in the threshold voltages on the output signals is considerably reduced.

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Eindhoven, Netherlands

Jan Lohstroh